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參數(shù)資料
| 型號(hào)： | STS4NM20N |
| 英文描述： | N-CHANNEL 200V 0.11 OHM 4A SO-8 ULTRA LOW GATE CHARGE MDMESH II MOSFET |
| 中文描述： | N溝道200伏0.11歐姆4A條的SO - 8超低柵極電荷的MDmesh MOSFET的二 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 138K |
| 代理商： | STS4NM20N |
3/6
STS4NM20N
ELECTRICAL CHARACTERISTICS
(CONTINUED)
DYNAMIC
Symbol
g
fs
(4)
C
iss
C
oss
C
rss
(*) C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
SWITCHING ON
Symbol
t
d(on)
t
r
SWITCHING OFF
Symbol
t
r (Voff)
t
f
t
c
SOURCE DRAIN DIODE
Symbol
I
SD
I
SDM
(2)
V
SD
(4)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Note: 1. When mounted on 1 inch
2
FR4 Board, 2oz of Cu, t
≤
10 sec.
2. Pulse width limited by safe operating area.
3. I
SD
≤
4 A, di/dt
≤
400 A/μs, V
DD
≤
V
(BR)DSS,
T
j
≤
T
jMAX.
4. Pulsed: Pulse duration = 400 μs, duty cycle 1.5 %.
Parameter
Test Conditions
V
DS
= 15 V , I
D
= 2 A
V
DS
= 25 V, f = 1 MHz, V
GS
= 0
Min.
Typ.
1.4
Max.
Unit
S
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Equivalent Output
Capacitance
Gate Input Resistance
670
180
12
pF
pF
pF
C
oss eq.
(*)
V
GS
= 0V, V
DS
= 0V to 400V
TBD
pF
R
G
f = 1 MHz Gate DC Bias = 0
Test Signal Level = 20 mV
Open Drain
TBD
Parameter
Test Conditions
V
DD
= 100 V, I
D
= 2 A
R
G
= 4.7
V
GS
= 10 V
(see test circuit, Figure 3)
V
DD
= 160 V, I
D
= 4 A,
V
GS
= 10 V
Min.
Typ.
TBD
TBD
Max.
Unit
ns
ns
Turn-on Delay Time
Rise Time
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
19
3.5
11
nC
nC
nC
Parameter
Test Conditions
Min.
Typ.
TBD
TBD
TBD
Max.
Unit
ns
ns
ns
Off-Voltage Rise Time
Fall Time
Cross-Over Time
V
DD
= 100 V, I
D
= 2 A,
R
G
= 4.7
,
V
GS
= 10 V
(see test circuit, Figure 3)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Source-drain Current
4
A
Source-drain Current (pulsed)
16
A
Forward On Voltage
I
SD
= 2 A, V
GS
= 0
I
SD
= 2 A, di/dt = 100 A/μs,
V
DD
= 100 V, T
j
= 25°C
(see test circuit, Figure 5)
1.3
V
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
89
300
6.5
ns
nC
A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 2 A, di/dt = 100 A/μs,
V
DD
= 100 V, T
j
= 150°C
(see test circuit, Figure 5)
TBD
TBD
TBD
ns
nC
A
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