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參數資料
| 型號： | SX18AC75DP |
| 英文描述： | IC-8-BIT MCU |
| 中文描述： | 集成電路8位微控制器 |
| 文件頁數： | 22/42頁 |
| 文件大小： | 312K |
| 代理商： | SX18AC75DP |
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1999 Scenix Semiconductor, Inc. All rights reserved.
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www.scenix.com
SX18AC / SX20AC / SX28AC
11.0
The device contains an on-chip differential comparator.
Ports RB0-RB2 support the comparator. Ports RB1 and
RB2 are the comparator negative and positive inputs,
respectively, while Port RB0 serves as the comparator
output pin. To use these pins in conjunction with the com-
parator, the user program must configure Ports RB1 and
RB2 as inputs and Port RB0 as an output. The CMP_B
register is used to enable the comparator, to read the
output of the comparator internally, and to enable the out-
put of the comparator to the comparator output pin.
The comparator enable bits are set to “1” upon reset,
thus disabling the comparator. To avoid drawing addi-
tional current during the power down mode, the compara-
tor should be disabled before entering the pwer down
mode. Here is an example of how to setup the compara-
tor and read the CMP_B register.
COMPARATOR
The final “mov” instruction in this example performs an
exchange of data between the working register (W) and
the CMP_B register. This exchange occurs only with Port
B accesses. Otherwise, the “mov” instruction does not
perform an exchange, but only moves data from the
source to the destination.
Fgure 11-1 shows the comparator block diagram.
CMP_B - Comparator Enable/Status Register
mov M,#$08
;set MODE register to access
;CMP_B
mov W,#$00
;clear W
mov !RB,W
;enable comparator and its
;output
...
;delay after enabling
;comparator for response
mov M,#$08
;set MODE register to access
;CMP_B
mov W,#$00
;clear W
mov !RB,W
;enable comparator and its
;output and also read CMP_B
;(exchange W and CMB_B)
and W,#$01
;set/clear Z bit based on
;comparator result
snb $03.2
;test Z bit in STATUS reg
;(0 => RB2<RB1)
jmp rb2_hi
;jump only if RB2>RB1
...
CMP_EN
Bit 7
CMP_OE
Bit 6
Reserved
Bits 5–1
CMP_RES
Bit 0
CMP_RES
Comparator result: 1 for RB2>RB1 or 0
for RB2<RB1. Comparator must be en-
abled (CMP_EN = 0) to read the result.
The result can be read whether or not the
CMP_OE bit is cleared.
When cleared to 0, enables the compar-
ator output to the RB0 pin.
When cleared to 0, enables the compar-
ator.
CMP_OE
CMP_EN
相關PDF資料 |
PDF描述 |
|---|---|
| SX18AC75SO | IC-SM-8-BIT MCU |
| SX18ACDP | IC-8-BIT MCU |
| SX18ACSO | IC-SM-8 BIT MCU |
| SX20AC100SO | IC-SM-8-BIT MCU |
| SXA-1 | Amplifier. Other |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SX18AC75-I/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/SS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
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