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參數(shù)資料
| 型號： | SX18AC75DP |
| 英文描述： | IC-8-BIT MCU |
| 中文描述： | 集成電路8位微控制器 |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 312K |
| 代理商： | SX18AC75DP |
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1999 Scenix Semiconductor, Inc. All rights reserved.
- 28 -
www.scenix.com
SX18AC / SX20AC / SX28AC
15.4
Direct Addressing
The FSR register must initialized with an appropriate
value in order to address the desired RAM register. The
following table and code example show how to directly
access the banked registers.
RAM Addressing
Indirect Addressing
To access any register via indirect addressing, simply
move the eight-bit address of the desired register into the
FSR and use INDF as the operand. The example below
shows how to clear all RAM locations from 10h to 1Fh in
all eight banks:
15.5
Often it is desirable to set the bank select bits of the FSR
register in one instruction cycle. The Bank instruction
provides this capability. This instruction sets the upper
bits of the FSR to point to a specific RAM bank without
affecting the other FSR bits.
Example:
The Bank Instruction
15.6
The instruction set contains instructions to set, reset, and
test individual bits in data memory. The device is capable
of bit addressing anywhere in data memory.
15.7
Input/Output Operation
The device contains three registers associated with each
I/O port. The first register (Data Direction Register), con-
figures each port pin as a Hi-Z input or output. The sec-
ond register (TTL/CMOS Register), selects the desired
input level for the input. The third register (Pull-Up Regis-
ter), enables a weak pull-up resistor on the pin configured
as a input. In addition to using the associated port regis-
ters, appropriate values must be written into the MODE
register to configure the I/O ports.
When two successive read-modify-write instructions are
used on the same I/O port with a very high clock rate, the
“write” part of one instruction might not occur soon
enough before the “read” part of the very next instruction,
resulting in getting “old” data for the second instruction.
To ensure predictable results, avoid using two succes-
sive read-modify-write instructions that access the same
port data register if the clock rate is high.
15.8
Increment/Decrement
The bank of 31 registers serves as a set of accumulators.
The instruction set contains instructions to increment and
decrement the register file. The device also includes both
INCSZ fr (increment file register and skip if zero) and
DECSZ fr (decrement file register and skip if zero)
instructions.
15.9
Loop Counting and Data Pointing
Testing
The device has specific instructions to facilitate loop
counting. The DECSZ fr (decrement file register and skip
if zero) tests any one of the file registers and skips the
next instruction (which can be a branch back to loop) if
the result is zero.
15.10
Branch and Loop Call Instructions
The device contains an 8-level hardware stack where the
return address is stored with a subroutine call. Multiple
stack levels allow subroutine nesting. The instruction set
supports absolute address branching.
15.10.1 Jump Operation
When a JMP instruction is executed, the lower nine bits
of the program counter is loaded with the address of the
specified label. The upper two bits of the program
counter are loaded with the page select bits, PA1:PA0,
contained in the STATUS register. Therefore, care must
be exercised to ensure the page select bits are pointing
to the correct page
before
the jump occurs.
15.10.2 Page Jump Operation
When a JMP instruction is executed and the intended
destination is on a different page, the page select bits
Bit Manipulation
Bank
0
1
2
3
4
5
6
7
FSR Value
010h
030h
050h
070h
090h
0B0h
0D0h
0F0h
mov
clr
FSR,#$070
$010
;Select RAM Bank 3
;Clear register 10h on
;Bank 3
;Select RAM Bank 6
;Clear register 10h on
;Bank 6
mov
clr
FSR,#$D0
$010
clr
FSR
;clear FSR to 00h (at address
;04h)
;set bit 4: address 10h-1Fh,
;30-3Fh, etc
;clear register pointed to by
;FSR
;increment FSR and test, skip
;jmp if 00h
;jump back and clear next
;register
:loop
setb SFR.4
clr
INDF
incsz FSR
jmp
:loop
bank
$F0
;Select Bank 7 in FSR
inc
$1F
;increment file register
;1Fh in Bank 7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SX18AC75-I/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/SS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX18AC75-I/TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
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