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參數(shù)資料
| 型號(hào)： | SX20AC100SO |
| 元件分類： | 8位微控制器 |
| 英文描述： | IC-SM-8-BIT MCU |
| 中文描述： | 集成電路釤8位微控制器 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 312K |
| 代理商： | SX20AC100SO |
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1999 Scenix Semiconductor, Inc. All rights reserved.
- 25 -
www.scenix.com
SX18AC / SX20AC / SX28AC
Note 1: The external Power-On Reset circuit is required
only if V
dd
power-up is too slow. The diode D helps dis-
charge the capacitor quickly when V
dd
powers down.
Note 2: R < 40 k
is recommended to make sure that
voltage drop across R does not violate the device electri-
cal specifications.
Note 3: R1 = 100
to 1k
will limit any current flowing
into MCLR from external capacitor C. This helps prevent
MCLR pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
13.0
The on-chip brown-out detection circuitry resets the
device when V
dd
dips below the specified brown-out volt-
age. The device is held in reset as long as V
dd
stays
below the brown-out voltage. The device will come out of
reset when V
dd
rises above the brown-out voltage. The
brown-out level is preset to approximately 4.2V at the
factory. The brown-out circuit can be disabled through
BOR0 and BOR1 bits contained in the FUSEX Word reg-
ister.
BROWN-OUT DETECTOR
Figure 12-3. Time-out Sequence on Power-up
(MCLR tied to V
dd
): Fast V
dd
Rise Time
Figure 12-4. Time-out Sequence on Power-up
(MCLR tied to V
dd
): Slow Rise Time
Figure 12-5. External Power-On Reset Circuit
(For Slow V
dd
Power-up)
V
dd
MCLR
POR
drt_time_out
RESET
Tdrt
V
dd
MCLR
POR
drt_time_out
RESET
Tdrt
V1
V
dd
R
C
MCLR
D
R1
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