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參數(shù)資料
| 型號(hào)： | SX8722I070TRLF |
| 廠商： | Semtech |
| 文件頁數(shù)： | 98/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ZOOMING ADC 10BIT 16CH 44MLPQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 壓力傳感器 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | I²C |
| 電流 - 電源： | 300µA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 44-MLPQ（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
| 配用： | XE8000EV120-ND - BOARD EVAL FOR SX8722I070TRLF |
| 其它名稱： | SX8722I070LFDKR |
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ACS - Revision 4.2
October 2008
2008 Semtech Corp.
www.semtech.com
Page 9
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8722
High gain acquisition for sensor interface
Notes
(1)
Gain defined as overall PGA gain GDTOT = GD1 x GD2 x GD3. Maximum input voltage is given by:
VIN,MAX = (VREF/2) (OSR/OSR+1).
(2)
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
(3)
Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS =
512 kHz. This figure must be multiplied by 2 for fS = 256 kHz, 4 for fS = 128 kHz. Input impedance is proportional to 1/fS.
(4)
Figure independent from PGA1 gain and sampling frequency fS. See equation Eq. 21 to calculate equivalent input noise.
(5)
Figure independent on PGA2 gain and sampling frequency fS. See equation Eq. 21 to calculate equivalent input noise.
(6)
Figure independent on PGA3 gain and sampling frequency fS. See equation Eq. 21 to calculate equivalent input noise.
(7)
Resolution is given by n = 2 log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be
set to 1, 2, 4 or 8.
(8)
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
(9)
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer
function (with the offset error removed).
(10)
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For 1 LSB offset, NELCONV must be
2.
(11)
INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds
over the full scale.
(12)
DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
(13)
Values for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage
changes.
(14)
Conversion time is given by: TCONV = (NELCONV (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2.
NELCONV can be set to 1, 2, 4 or 8.
(15)
PGAs are reset after each writing operation to registers CxRegAdc1-5. The ADC must be started after a PGA or inputs common-
mode stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching.
Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number
of cycles. This delay does not apply to conversions made without the PGAs.
(16)
Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = '11' and IB_AMP_ADC[1:0] = '11'.
(17)
Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '10', IB_AMP_ADC[1:0] = '10'.
(18)
Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = '01', IB_AMP_ADC[1:0] = '01'.
(19)
Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '00', IB_AMP_ADC[1:0] = '00'.
Not
Recommended
for
New
Designs
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