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參數(shù)資料
| 型號(hào)： | SY100E337JZTR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| 中文描述： | 100E SERIES, 3-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 75K |
| 代理商： | SY100E337JZTR |
1
SY10E337
SY10E337
SY100E337
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
FEATURES
I
1500ps max. clock to bus (data transmit)
I
1000ps max. clock to Q (data receive)
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
25
cutoff bus outputs
I
50
receiver outputs
I
Scannable implementation of E336
I
Synchronous and asynchronous bus enables
I
Non-inverting data path
I
Bus outputs feature internal edge slow-down
capacitors
I
Additional package ground pins
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E337
I
Available in 28-pin PLCC package
3-BIT SCANNABLE
REGISTERED BUS
TRANSCEIVER
DESCRIPTION
The SY10/100E337 are 3-bit registered bus transceivers
with scan designed for use in new, high- performance ECL
systems. The bus outputs (BUS
0
–BUS
2
) are designed to
drive a 25
bus; the receive outputs (Q
0
–Q
2
) are designed
for 50
. The bus outputs feature a normal logic HIGH level
(V
OH
) and a cutoff LOW level of –2.0V and the output
emitter-follower is “off”, presenting a high impedance to the
bus. The bus outputs also feature edge slow-down
capacitors.
Both drive and receive sides feature the same logic,
including a loopback path to hold data. The LOAD/HOLD
function is controlled by Transmit Enable (TEN) and Receive
Enable (REN) on the transmit and receive sides,
respectively, with a HIGH selecting LOAD. The
implementation of the E337 Receive Enable differs from
that of the E336.
A synchronous bus enable (SBUSEN) is provided for
normal, non-scan operation. The asynchronous bus disable
(ABUSDIS) disables the bus for scan mode.
The SYNCEN input allows either synchronous or
asynchronous re-enabling after disabling with ABUSDIS.
An alternative use is asynchronous-only operation with
ABUSDIS, in which case SYNCEN is tied LOW. SYNCEN
is implemented as an overriding SET control to the enable
flip-flop.
Scan mode is selected by a logic HIGH at the SCAN
input. Scan input data is shifted in through S-IN, and output
data appears at the Q
2
output.
All registers are clocked on the rising edge of CLK.
Additional lead-frame grounding is provided through the
ground pins (GND) which should be connected to 0V. The
GND pins are not electrically connected to the chip.
Pin
Function
A
0
–A
2
Data Inputs A
B
0
–B
2
Data Inputs B
S-IN
Serial (Scan) Data Input
TEN, REN
LOAD/HOLD Controls
SCAN
Scan Control
ABUSDIS
Asynchronous Bus Disable
SBUSEN
Synchronous Bus Enable
SYNCEN
Synchronous Enable Control
CLK
Clock
25
Cutoff BUS Outputs
Receive Data Outputs (Q
2
serves as
SCAN_OUT in scan mode)
BUS
0
–BUS
2
Q
0
–Q
2
V
CCO
V
CC
to Output
PIN NAMES
Rev.: F
Issue Date:
Amendment: /0
March 2006
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| SY100E404 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:QUAD DIFFERENTIAL AND/NAND |
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| SY100E404JC TR | 功能描述:IC GATE AND/NAND QUAD 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 柵極和逆變器 - 多功能，可配置 系列:100E 產(chǎn)品變化通告:Product Obsolescence 05/Oct/2010 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯類型:可配置多功能 電路數(shù):2 輸入數(shù):2 施密特觸發(fā)器輸入:無 輸出類型:差分 輸出電流高，低:- 電源電壓:2.375 V ~ 3.465 V 工作溫度:-40°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-LBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:16-FCBGA（4x4） 包裝:帶卷 (TR) |
| SY100E404JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:QUAD DIFFERENTIAL AND/NAND |
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