參數(shù)資料
型號(hào): SY10E404JC
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: QUAD DIFFERENTIAL AND/NAND
中文描述: 10E SERIES, QUAD 2-INPUT AND/NAND GATE, PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 60K
代理商: SY10E404JC
DESCRIPTION
FEATURES
I
Differential D and Q
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
700ps max. propagation delay
I
High frequency outputs
I
Internal 75K
input pull-down resistors
I
Fully compatible with Motorola 10E/100E404
I
Available in 28-pin PLCC package
The SY10/100E404 are 4-bit differential AND/NAND
devices. The differential operation of these devices make
them ideal for pulse shaping applications where duty cycle
skew is critical. Special design techniques were
incorporated to minimize the skew between the upper
and lower level gate inputs.
Because a negative 2-input NAND function is
equivalent to a 2-input OR function, the differential inputs
and outputs of the devices also allow for their use as
fully differential 2-input OR/NOR functions.
The output RISE/FALL times of these devices are
significantly faster than most other standard ECLinPS
devices, resulting in an increased bandwidth.
The differential inputs have clamp structures which
will force the Q output of a gate in an open input condition
to go to a LOW state. Thus, inputs of unused gates can
be left open and will not affect the operation of the rest
of the device.
QUAD DIFFERENTIAL
AND/NAND
Rev.: D
Issue Date: February, 1998
Amendment: /1
SY10E404
SY100E404
BLOCK DIAGRAM
D
0a
D
0a
D
0b
D
0b
Q
0
Q
0
D
1a
D
1a
D
1b
D
1b
Q
1
Q
1
D
2a
D
2a
D
2b
D
2b
Q
2
Q
2
D
3a
D
3a
D
3b
D
3b
Q
3
Q
3
PIN CONFIGURATION
Pin
Function
D[0:4], D[0:4]
Differential Data Inputs
Q[0:4], Q[0:4]
Differential Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
18
17
16
15
14
13
12
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23 22 21 20 19
D
2b
D
2a
V
EE
D
2a
D
1b
D
2b
D
1b
Q
2
V
CC
Q
1
Q
1
Q
0
Q
0
Q
2
D
0
D
0
V
C
D
1
D
1
D
0
D
0
Q
3
D
3
D
3
D
3
V
C
D
3
Q
3
1
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