參數資料
型號: SY100E452JY TR
廠商: Micrel Inc
文件頁數: 1/4頁
文件大?。?/td> 0K
描述: IC REGISTER 5BIT DIFF 28-PLCC
標準包裝: 750
系列: 100E
功能: 主復位
類型: D 型總線
輸出類型: 差分
元件數: 1
每個元件的位元數: 5
頻率 - 時鐘: 1.4GHz
觸發(fā)器類型: 正邊沿
電源電壓: 4.2 V ~ 5.5 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
包裝: 帶卷 (TR)
其它名稱: SY100E452JYTR
SY100E452JYTR-ND
1
SY10E452
SY100E452
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
D [0:4], /D [0:4]
Differential Data Inputs
MR
Master Reset Input
CLK, /CLK
Differential Clock Input
VBB
VBB Reference Output
Q [0:4], Q [0:4]
Differential Data Outputs
VCCO
VCC to Output
DESCRIPTION
FEATURES
s Differential D, CLK and Q
s Extended 100E VEE range of –4.2V to –5.5V
s VBB output for single-ended use
s 1100MHz min. toggle frequency
s Asynchronous Master Reset
s Fully compatible with Motorola MC10E/100E452
s Available in 28-pin PLCC package
The SY10/100E452 are 5-bit differential registers with
differential data (inputs and outputs) and clock. The
registers are triggered by a positive transition of the
positive clock (CLK) input. A high on the Master Reset
(MR) asynchronously resets all registers so that the Q
outputs go LOW.
The differential input structures are clamped so that
the inputs of unused registers can be left open without
upsetting the bias network of the devices. The clamping
action will assert the /D and the /CLK sides of the inputs.
Because of the edge-triggered flip-flop nature of the
devices, simultaneously opening both the clock and data
inputs will result in an output which reaches an
unidentified but valid state.
The fully differential design of the devices makes them
ideal for very high frequency applications where a
registered data path is necessary.
5-BIT DIFFERENTIAL
REGISTER
SY10E452
SY100E452
BLOCK DIAGRAM
D0
Q0
VBB
CLK
D
Q
R
MR
D1
Q1
D
Q
R
D2
Q2
D
Q
R
D3
Q3
D
Q
R
D4
Q4
D
Q
R
PIN NAMES
Rev.: F
Amendment: /0
Issue Date:
March 2006
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