參數(shù)資料
型號(hào): SY100EP56VK4G TR
廠商: Micrel Inc
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 0K
描述: IC MUX DUAL DIFF 3.3V/5V 20TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: 100EP
類型: 多路復(fù)用器
電路: 2 x 2:1
獨(dú)立電路: 1
電壓電源: 雙電源
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
其它名稱: SY100EP56VK4GTR
SY100EP56VK4GTR-ND
2
ECL Pro
SY100EP56V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTION
Pin
Pin Number
Function
D0a, /D0a
1, 2,
Channel 0 PECL/ECL differential signal inputs. Multiplexing of these two differential inputs is
D0b, /D0b
4, 5
controlled by SEL0, or COM_SEL. The signal inputs include internal 75k pull-down resistors.
Default condition is LOW when left floating. The input signal should be terminated externally.
See “
Termination” section
D1a, /D1a
6, 7
Channel 1 PECL/ECL differential signal inputs. Multiplexing of these two differential inputs is
D1b, /D1b
9, 10
controlled by SEL1, or COM_SEL. The signal inputs include internal 75k pull-down resistors.
Default condition is a logic LOW when left floating. The input signal should be terminated
externally. See “
Termination” section
VBB0, VBB1
3, 8
Channel 0 and Channel 1 reference output voltage. This reference is typically used to bias the
unused inverting input for single-ended input applications, or as the termination point for AC–
coupled differential input applications. V
BB reference value is approximately VCC –1.4V, and tracks
V
CC 1:1. Maximum sink/source capability is 0.50mA. For single ended PECL inputs, connect to
the unused input through a 50 resistor. Decouple the VBB pin with a 0.01F capacitor. For PECL/
LVPECL inputs, the decoupling capacitor is connected to V
CC, since PECL signals are referenced
to V
CC. Leave floating if not used.
VEE
11
Negative Power Supply: For PECL/LVPECL applications, connect to GND.
/Q1, Q1
12, 13
Channel 1 100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50
resistor to V
CC–2V. Unused output pairs may be left floating. Unused single-ended outputs must
have a balanced load. For AC-coupled applications, the output stage emitter follower must have a
DC current path to ground. See “
Termination” section.
SEL1, SEL0
15, 17
100KEP PECL/ECL compatible Channel 1 and Channel 0 MUX select control. See “
MUX Select
Truth Table.” Each pin includes an internal 75k pull-down resistor. Default condition when left
floating is LOW.
COM_SEL
16
100KEP PECL/ECL compatible Channel 1 and Channel 0 Common MUX select control. This is
the common select control pin for both Channels 0 and 1. Includes an internal 75k pull-down
resistor. Default condition when left floating is LOW. Leave floating when not used.
/Q0, Q0
18, 19
Channel 0 100K EP PECL/ECL compatible differential output. PECL/ECL termination is with a
50 resistor to VCC –2V. Unused output pairs may be left floating. Unused single-ended outputs
must have a balanced load. For AC–coupled applications, the output stage emitter follower must
have a DC current path to ground. See “
Termination” section.
VCC
14, 20
Positive Power Supply: Both V
CC pins must be connected to the same power supply externally.
Bypass with 0.1F//0.01F low ESR capacitors.
PACKAGE/ORDERING INFORMATION
20-Pin TSSOP (K4-20-1)
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY100EP56VK4I
K4-20-1
Industrial
XEP56V
Sn-Pb
SY100EP56VK4ITR(2)
K4-20-1
Industrial
XEP56V
Sn-Pb
SY100EP56VK4G(3)
K4-20-1
Industrial
XEP56V with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY100EP56VK4GTR(2, 3)
K4-20-1
Industrial
XEP56V with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
VBB0
D0b
/D0b
D1a
/D1a
VBB1
D1b
/D1b
18 /Q0
SEL0
COM_SEL
SEL1
VEE
17
16
15
14
13
12
11
19
20
1
2
3
4
5
6
7
8
9
10
D0a
/D0a
/Q1
Q1
VCC
Q0
VCC
1
0
1
0
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