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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� SY100EP56VK4G TR
寤犲晢锛� Micrel Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 3/8闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MUX DUAL DIFF 3.3V/5V 20TSSOP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
绯诲垪锛� 100EP
椤炲瀷锛� 澶氳矾寰�(f霉)鐢ㄥ櫒
闆昏矾锛� 2 x 2:1
鐛�(d煤)绔嬮浕璺細 1
闆诲闆绘簮锛� 闆欓浕婧�
闆绘簮闆诲锛� 3 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-TSSOP
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� SY100EP56VK4GTR
SY100EP56VK4GTR-ND
3
ECL Pro
SY100EP56V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Symbol
Rating
Value
Unit
VCC 鈥擵EE
Power Supply Voltage
6.0
V
VIN
Input Voltage (VCC = 0V, VIN not more negative than VEE)
鈥�6.0 to 0
V
Input Voltage (VEE = 0V, VIN not more positive than VCC)
+6.0 to 0
V
IOUT
Output Current
鈥揅ontinuous
50
mA
鈥揝urge
100
IBB
VBB Sink/Source Current
(2)
卤0.5
mA
TLEAD
Lead Temperature (soldering, 20sec.)
+260
掳C
TA
Operating Temperature Range
鈥�40 to +85
掳C
Tstore
Storage Temperature Range
鈥�65 to +150
掳C
JA
Package Thermal Resistance
鈥揝till-Air (single-layer PCB)
115
掳C/W
(Junction-to-Ambient)
鈥揝till-Air (multi-layer PCB)
75
鈥�500lfpm (multi-layer PCB)
65
JC
Package Thermal Resistance
21
掳C/W
(Junction-to-Case)
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended
periods may affect device reliability.
2. Due to the limited drive capability, the V
BB reference should only be used for inputs from the same package device (i.e., do not use for other
devices).
ABSOLUTE MAXIMUM RATINGS(1)
TA = 鈥�40CTA = +25CTA = +85C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
VCC
Power Supply Voltage
V
(PECL)
4.5
5.0
5.5
4.5
5.0
5.5
4.5
5.0
5.5
(LVPECL)
3.0
3.3
3.8
3.0
3.3
3.8
3.0
3.3
3.8
(ECL)
鈥�5.5
鈥�5.0
鈥�4.5
鈥�5.5
鈥�5.0
鈥�4.5
鈥�5.5
鈥�5.0
鈥�4.5
(LVECL)
鈥�3.8
鈥�3.3
鈥�3.0
鈥�3.8
鈥�3.3
鈥�3.0
鈥�3.8
鈥�3.3
鈥�3.0
IEE
Supply Current
鈥�
50
65
鈥�
50
65
鈥�
50
65
mA
No Load
IIH
Input HIGH Current
鈥�
150
鈥�
150
鈥�
150
AVIN = VIH
IIL
Input LOW Current
All Inputs
0.5
鈥�
0.5
鈥�
0.5
鈥�
AVIN = VIL
CIN
Input Capacitance (TSSOP)
鈥斺€斺€斺€�
1.0
鈥斺€斺€斺€�
pF
Note:
1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.
DC ELECTRICAL CHARACTERISTICS(1)
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