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參數(shù)資料
| 型號： | SY55856UHG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 7TAP 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | SuperLite&trade |
| 標(biāo)片/步級數(shù)： | 7 |
| 功能： | 多個，不可編程 |
| 延遲到第一抽頭： | 50ps |
| 接頭增量： | 50ps |
| 可用的總延遲： | 350ps |
| 獨(dú)立延遲數(shù)： | 2 |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1088 (CN2011-ZH PDF) |
| 其它名稱： | 576-2046 SY55856UHG-ND |
4
SuperLite
SY55856U
Micrel, Inc.
M9999-021908
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
The true pin of a CML input pair is internally biased to
ground through a 75k resistor. The complement pin of a
CML input pair is internally biased halfway between V
CC
and ground by a voltage divider consisting of two 75k
resistors. To keep a CML input at static logic zero at V
CC >
3.0V, leave both inputs unconnected. For V
CC ≤ 3.0V,
connect the complement input to V
CC and leave the true
input unconnected. To make an input static logic one,
connect the true input to V
CC, and leave the complement
input unconnected. These are the only safe ways to cause
CML inputs to be at a static value. In particular, no CML
input should be directly connected to ground. All NC pins in
the figures below should be left unconnected.
VT (Variable Threshold) Inputs
Five inputs to SY55856U, CINV, DELAY_SEL, S0, S1, and
S2, are variable threshold inputs. The LVL input determines
the Voltage threshold that differentiates logic high from logic
low for these five inputs only. If LVL is left unconnected, the
VT inputs will switch at about
V
GND
2
CC +
or V
TCL,
whichever is higher. To obtain a logic switching threshold
different from this, the LVL input must be driven with the
actual desired threshold voltage. The user may drive the
LVL pin with any voltage between V
CC – 0.1V and ground.
For example, driving LVL with a voltage set at Vcc – 1.3V
causes the VT inputs to accept single ended PECL outputs
and switch appropriately.
Note that VT inputs are internally clamped so that the
threshold will not fall below VTCL Volts. Since driving the
LVL input to ground causes the threshold to be somewhere
between V
TCL (min) and VTCL (max), it is expected that the
user will keep the Voltage at the LVL pin at or above V
TCL
(max). Please refer to Figure 3 for clarification.
VCC
NC
IN
/IN
Figure 1. Hard Wiring a Logic "1"(1)
NC
VCC > 3.0V
NC
IN
/IN
NC
VCC ≤ 3.0V
VCC
IN
/IN
Figure 2. Hard Wiring a Logic "0"(1)
Operating
Range
VTCL
VCC – 0.1V
VCC
LVL
Input
Logic
Switching
Threshold
Figure 3a. Logic Switching Threshold
3
VCC
3.0V ≤ VCC ≤ 3.6V
SY55856
909
1.10k
S0, S1, S2
LVL
TTL
Driver
VCC
Figure 3b. Interfacing TTL-to-CML Select
(CINV, DELAY_SEL, S0, S1, S2)
Note 1.
IN is either the DATA_IN or the CLK_IN input. /IN is either the /
DATA_IN or the /CLK_IN input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY55856UHG TR | 功能描述:延遲線/計時元素 2.5V/3.3V 2.5GHz 2 Channel Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY55856UHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE |
| SY55856UHI | 功能描述:IC DELAY LINE 7TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:SuperLite&trade 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY55856UHI TR | 功能描述:IC DELAY LINE 7TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:SuperLite&trade 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY55856UHITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE |
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