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參數(shù)資料
型號: SY55856UHG
廠商: Micrel Inc
文件頁數(shù): 7/9頁
文件大?。?/td> 0K
描述: IC DELAY LINE 7TAP 32-TQFP
標準包裝: 250
系列: SuperLite&trade
標片/步級數(shù): 7
功能: 多個,不可編程
延遲到第一抽頭: 50ps
接頭增量: 50ps
可用的總延遲: 350ps
獨立延遲數(shù): 2
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-EPAD-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 1088 (CN2011-ZH PDF)
其它名稱: 576-2046
SY55856UHG-ND
7
SuperLite
SY55856U
Micrel, Inc.
M9999-021908
hbwhelp@micrel.com or (408) 955-1690
TA = –40°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
VCC
Power Supply Voltage
2.3
3.6
2.3
3.6
2.3
3.6
V
ICC
Power Supply Current
140
115
140
140
mA
No Load
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
VILVL
Analog Input(2)
VTCL
—VCC - 0.1
V
VIHVT
VT Input High Voltage(3,4)
VSW + 0.1
VCC
V
VILVT
VT Input High Voltage(3,4)
0.0
VSW – 0.1
V
IST
Input Switching Threshold
100
50
mV
Differential Voltage(5)
VTCL
Threshold Clamp Voltage
1.2
1.4
V
VT INPUTS DC ELECTRICAL CHARACTERISTICS
VCC = 2.3V to 3.6V; GND = 0V; TA = –40°C to +85°C
(1)
Note 1.
DC parameters are guaranteed after thermal equilibrium has been established.
Note 2.
The LVL input determines the voltage switching threshold that differentiates logic high from logic low for the V
T inputs S0, S1, S2,
DELAY_SEL, and CINV. LVL may be driven to V
CC, but this is not useful, as the VT inputs could then not get high enough to reliably indicate
logic high. Also, as shown in Figure 3, the LVL input internally clamps at V
TCL. If LVL is left unconnected, the VT inputs will switch at about the
maximum of
V
GND
2
CC +
=
V
CC
2
and V
TCL.
Note 3.
V
T inputs are S0, S1, S2, DELAY_SEL, and CINV.
Note 4.
V
SW is the threshold switching voltage. It is equal to the voltage at the LVL pin, when this voltage is above VTCL (max). VSW is some value
between V
TCL (min) and VTCL (max) when the Voltage at the LVL pin is below VTCL (max).
Note 5.
V
IST is the voltage difference needed to guarantee a stable logic level. Logic high must be at least VIST above VSW. Logic low must be at most
V
IST below VSW. Thus, the minimum input swing on a given VT input pin, that is, |VIHVT - VILVT|, must be at least 2×VIST.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
V
ID
Differential Input Voltage
100
mV
V
IH
Input HIGH Voltage
1.6
V
CC
V
IL
Input LOW Voltage
1.5
V
IH –0.1
V
OH
Output HIGH Voltage
V
CC –0.040
V
CC –0.010
V
CC
V
No Load
V
OL
Output LOW Voltage
V
CC –1.00
V
CC –0.800
V
CC –0.65
V
No Load
V
OUT
Output Voltage Swing(6)
0.650
0.800
1.00
V
No Load
(Swing)
0.400
50 Environment
R
OUT
Output Source Impedance
40
50
60
(CLK_OUT, /CLK_OUT and
DATA_OUT, /DATA_OUT)
CML DC ELECTRICAL CHARACTERISTICS
VCC = 2.3V to 3.6V; GND = 0V; TA = –40°C to +85°C
Note 6.
V
OUT(SWING) is defined as the swing on one output of a differential pair, that is |VOH - VOL| on one pin. The swing for common mode noise
immunity purposes is 2 × VOUT(SWING). Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a
400mV swing is available in a 50 environment. Refer to “CML Termination” figures for more details.
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