參數(shù)資料
型號: SY58051UMG
廠商: Micrel Inc
文件頁數(shù): 1/10頁
文件大小: 0K
描述: IC GATE CML UNIV I/O TERM 16MLF
標準包裝: 100
系列: SY58
邏輯類型: 可配置多功能
電路數(shù): 1
輸入數(shù): 2
施密特觸發(fā)器輸入:
輸出類型: 差分
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應商設備封裝: 16-MLF?(3x3)
包裝: 托盤
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1398
SY58051U
Ultra-Precision CML AnyGate
with Internal Input and Output Termination
Precision Edge
AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
July 2011
M9999-071311U-A
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY58051U is an ultra-fast, low jitter universal logic
gate with a guaranteed maximum data or clock
throughput of 10.7Gbps or 7GHz, respectively. This
AnyGate
differential logic device will produce many
logic functions of two Boolean variables, such as AND,
NAND, OR, NOR, DELAY, or NEGATION.
The SY58051U differential inputs include a unique
internal termination design that allows access to the
termination network throughout a VT pin. This feature
allows the device to easily interface to different logic
standards, both AC- and DC-coupled without external
resistor-bias and termination networks. The result is a
clean, stub-free, low-jitter interface solution. The
differential CML output is optimized for environments
with internal 50 source termination and a 400mV
output swing.
The SY58051U operates from a 2.5 or 3.3V supply, and
is guaranteed over the full industrial temperature range
(-40°C to +85°C). The SY58051U is part of Micrel’s
Precision Edge
product family.
All support documentation can be found on Micrel’s web
Typical Application
Precision Edge
Features
Three matched-delay input pair provide any logic
function: AND, NAND, OR, NOR
Guaranteed AC performance over temperature and
voltage:
DC to > 10.7Gbps data rate throughput
DC to > 7GHz clock fMAX
<190ps Any In-to-Out tpd
tr / tf < 60ps
Ultra low-jitter design:
<1psRMS random jitter
<10psPP deterministic jitter
<10psPP total jitter (clock)
Unique input termination and VT pin accepts DC-
coupled and AC-coupled inputs (CML, PECL)
Internal 50 output source termination
Typical 400mV CML output swing (R
IN
= 50
)
Internal 50 input termination
Power supply 2.5V ±5% or 3.3V ±10%
–40°C to 85°C temperature range
Available in a 16-pin (3mm × 3mm) QFN package
Applications
Data communication systems
OC-192, OC192+FEC
All SONET OC-3—OC-768 applications
All Fibre Channel applications
All GigE applications
相關PDF資料
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TXR54AB00-2008AI ADPTR TINEL LOCK STR SHELL 20,37
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