參數(shù)資料
型號: SY58620LMG TR
廠商: Micrel Inc
文件頁數(shù): 14/18頁
文件大?。?/td> 0K
描述: TXRX 4.25GBPS CML OUT 24-MLF
標準包裝: 1,000
類型: 收發(fā)器
驅動器/接收器數(shù): 1/1
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應商設備封裝: 24-MLF?(4x4)
包裝: 帶卷 (TR)
其它名稱: SY58620LMGTR
SY58620LMGTR-ND
Micrel, Inc.
SY58620L
January 2006
5
M9999-012006-C
hbwhelp@micrel.com or (408) 955-1690
Outputs
Pin Number
Pin Name
Pin Description
22
LOS
Loss-of-Signal Output. TTL-compatible output with internal 4.75k
pull-up resistor. Loss-of-
Signal asserts to logic HIGH when the receiver input amplitudes falls below the threshold set
by LOSLVL.
19
LOSLVL
RX Loss-of-Signal Level Set. A resistor (RLOSLVL) connected between LOSLVL and VCC sets
the threshold for the data input amplitude at which the LOS output is asserted. Default is max
sensitivity. LOSLVL is used to set the Loss-of-Signal (LOS) voltage. It is internally connected
to a 2.8k
pull-down resistor to an internal V
REF voltage source. See “Typical Operating
Characteristics,” and “Application Implementation” sections for more details.
17, 16
RXQ, /RXQ
Receiver Differential Output. Output is CML compatible. Refer to the “Truth Table” and
“Output Stage” sections for more details. Unused output pair may be left open. The output is
designed to drive 400mV (800mVPP) into 50 to VCC or 100 across the pair.
5, 6
TXQ, /TXQ
Transmitter Differential Variable Swing Output. Output is CML compatible. Please refer to the
“Truth Table” and “Output Stage” sections for more details. Unused output pair may be left
open. The output is designed to drive 80mV (160mVPP) min swing to 400mV (800mVPP) typ.
swing into 50
to V
CC_TXQ or drive 100 across the pair depending on TXVCTRL.
8
VREF_CTRL
Transmitter Output Reference Voltage. Output biases to VCC_TXQ-1.3V. Connecting VREF_CTRL
to TXVCTRL sets the transmitter output swing to max swing.
10
TXVREF-AC
Transmitter Input Reference Voltage. This output biases to VCC-1.3V. It is used when AC
coupling the transmitter input. For AC-coupled applications, connect TXVREF-AC to the
TXVT pin and bypass with a 0.01F low ESR capacitors to VCC. See “Input Stage” section for
more details. Maximum sink/source current is ±1.5mA.
Power Pins
Pin Number
Pin Name
Pin Description
3, 24
GND,
Exposed Pad
Ground. GND pins and exposed pad must be connected to the same ground plane.
12, 15, 18
VCC
3.3V ±10% Positive Power Supply. Bypass with 0.1F//0.01F low ESR capacitors and place
as close to each VCC pins as possible. Power pins are not connected internally and must be
connected to the same power supply externally.
21
VCC_RXIN
3.3V ±10% Receive Input Power Supply. Bypass with 0.1F//0.01F low ESR capacitors and
place as close to the VCC_RXIN pin as possible. Power pins are not connected internally and
must be connected to the same power supply externally.
4
VCC_TXQ
3.3V ±10% Output Transmit Power Supply. Bypass with 0.1F//0.01F low ESR capacitors
and place as close to the VCC_TXQ pin as possible. Power pins are not connected internally
and must be connected to the same power supply externally.
Truth Table
LOOPBACK
RXQ
TXQ
0
RXIN
TXIN
1
TXIN
RXIN
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