參數(shù)資料
型號: SY69753LHG TR
廠商: Micrel Inc
文件頁數(shù): 12/13頁
文件大?。?/td> 0K
描述: IC CLOCK/DATA REC 155MBPS 32TQFP
標準包裝: 1,000
類型: 時鐘和數(shù)據(jù)恢復(CDR),多路復用器
PLL:
主要目的: 以太網,SONET/SDH,ATM OC-3
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 155Mbps
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP 裸露焊盤
供應商設備封裝: 32-EPAD-TQFP
包裝: 帶卷 (TR)
其它名稱: SY69753LHGTR
SY69753LHGTR-ND
MCP7940M
DS22292A-page 8
Preliminary
2012 Microchip Technology Inc.
FIGURE 3-2:
ACKNOWLEDGE TIMING
3.1.2
DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’. The RTCC registers and
the SRAM share the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The next byte received defines the address of
the data byte (Figure 3-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7940M monitors
the SDA bus, checking the device type identifier being
transmitted. Upon receiving a ‘1101111’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
MCP7940M will select a read or write operation.
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
SCL
9
8
7
6
5
4
3
2
11
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
1
101
R/W
X
A
0
SRAM RTCC CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
111
X = Don’t Care
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