參數(shù)資料
型號(hào): SY69753ALHG TR
廠商: Micrel Inc
文件頁(yè)數(shù): 1/13頁(yè)
文件大小: 0K
描述: IC CLOCK/DATA REC 125MBPS 32TQFP
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,ATM OC-3
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 155Mbps
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-EPAD-TQFP
包裝: 帶卷 (TR)
其它名稱(chēng): SY69753ALHGTR
SY69753ALHGTR-ND
SY69753AL
3.3V, 125Mbps, 155Mbps Clock
and Data Recovery
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
August 2007
M9999-082107-E
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY69753AL is a complete Clock Recovery and
Data Retiming integrated circuit for OC-3/STS-3
applications at 155Mbps NRZ. The device is ideally
suited for SONET/SDH/ATM applications and other
high-speed data transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
The SY69753AL also includes a link fault detection
circuit.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
3.3V power supply
SONET/SDH/ATM compatible
Clock and data recovery for 125Mbps/155Mbps NRZ
data stream
Two on-chip PLLs: one for clock generation and
another for clock recovery
Selectable reference frequencies
Differential PECL high-speed serial I/O
Line receiver input: no external buffering needed
Link fault indication
100k ECL compatible I/O
Industrial temperature range (–40°C to +85°C)
Lower power: fully compatible with Micrel’s
SY87701V, but with 30% less power
Available in 32-pin EPAD-TQFP
Applications
Ethernet media converter(m)
SONET/SDH/ATM OC-3
Proprietary architecture at 120Mbps to 180Mbps
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