CML OUTPUT DIAGRAM
參數(shù)資料
型號(hào): SY87721LHY TR
廠(chǎng)商: Micrel Inc
文件頁(yè)數(shù): 15/16頁(yè)
文件大小: 0K
描述: IC CLOCK/DATA RECOVERY 64-TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: AnyRate®
類(lèi)型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,ATM 應(yīng)用
輸入: PECL
輸出: CML,PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.7GHz
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 帶卷 (TR)
其它名稱(chēng): SY87721LHYTR
SY87721LHYTR-ND
SY87721L
8
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
LOOP FILTER COMPONENTS
CML OUTPUT DIAGRAM(1)
50
50
100
SY87721L
VCC
16mA
Figure 3.
50
Load CML Output
PLLSN+
or
PLLSW+
PLLSN–
or
PLLSW–
RC
Figure 1. Narrow Band and Wide Band
Synthesizer Loop Filter
PLLRN+
or
PLLRW+
PLLRN–
or
PLLRW–
R
C
Figure 2. Narrow Band and Wide Band
CDR Loop Filter
NOTE:
1. V
OSW is defined as |VOH–VOL| on any one pin (either the true or the
complement pin). As opposed to the single-ended swing, differential
swing, V
OSW (true pin) + VOSW (complement pin) is double the VOSW
value.
OC-48 JITTER TRANSFER AND TOLERANCE
OC-48 Jitter Tolerance
.1
1
10
100
1000
10000
100000
1.E+6
1.E+7
Modulation Frequency (Hz)
Amplitude
UI
OC-48 Jitter Transfer
-20
-10
0
10
1000
10000
100000
1.E+6
1.E+7
Modulation Frequency (Hz)
Jitter
Ratio
(dB)
PLL
R
C
PLLSN+, PLLSN–
1.2k
1
F
PLLRN+, PLLRN–
390
1
F
PLLSW+, PLLSW–
845
1
F
PLLRW+, PLLRW–
455
1
F
Table 4. Synthesizer and Clock Recovery Loop Filter Values
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