參數(shù)資料
型號: SY87721LHY TR
廠商: Micrel Inc
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY 64-TQFP
標準包裝: 1,000
系列: AnyRate®
類型: 時鐘和數(shù)據(jù)恢復(CDR),多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,ATM 應用
輸入: PECL
輸出: CML,PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.7GHz
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應商設備封裝: 64-TQFP-EP(10x10)
包裝: 帶卷 (TR)
其它名稱: SY87721LHYTR
SY87721LHYTR-ND
SY87721L
12
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
EVALUATION BOARD SCHEMATIC
SY87721L
2
3
4
5
6
7
8
9
10
11
12
13
17
48
47
46
45
44
43
42
41
40
39
38
37
36
61
60
59
58
57
56
55
54
53
52
51
50
14
15
16
35
34
33
62
63
64
RDIN+
GND
VCC
REFCLK
REFCLK+
GND
VCC
GND
DIVSEL3
ALRSEL
CLKSEL
GND
DIVSEL1
DIVSEL2
NC
RDIN
LFIN
BRD+
BRD
VCCO
VCC
BRDMX
GND
VCC
GND
CD
FREQSEL3
FREQSEL2
FREQSEL1
VCOSEL2
TCLKC—
TCLKC+
TCLKE—
TCLKE+
VCCO
RCLKC—
RCLKC+
RCLKE—
RCLKE+
VCCO
RDOUTC—
RDOUTC+
RDOUTE—
RDOUTE+
ENPECL
GND
VCOSEL1
PLLRN+
PLLRN—
NC
PLLRW+
PLLRW—
NC
VCCA
GNDA
PLLSW—
PLLSW+
NC
PLLSN—
PLLSN+
NC
1
49
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
67
8
9
10
11
12
VEE
VCCO: PIN 37
VCCO: PIN 42
RDOUTE+
RDOUTE—
RDOUTC+
RDOUTC—
RCLKE+
RCLKE—
RCLKC+
RCLKC—
TCLKE+
TCLKE—
TCLKC+
TCLKC—
VEE: PIN 48
VCC
VEE
VEE:PIN
32
VEE:PIN
26
VEE:PIN
25
REFCLK+:
FORCE
REFCLK+:
SENSE
VCC
L4
C11
C12
VEE
VCCA
L3
C10
C9
VEE:PIN
23
REFCLK
:FORCE
REFCLK
:SENSE
SW DIP-6
S3
1
3
5
7
9
11
12
10
8
6
4
2
HEADER
6X2
JP1
VCC
1
2
3
4
56
7
8
9
10
VEE
SW DIP-5
S1
R5,
5k
VCC
C5
R7
C6
R8
C7
R9
C8
R10
RDIN+:
FORCE
RDIN+:
SENSE
RDIN
:FORCE
RDIN
:SENSE
BRD+:
PIN
52
BRD
:PIN
53
VEE:
PIN
57
VCC:
PIN
58
VCC
L2
C3
C4
1
3
56
4
2
HEADER
3X2
JP4
LED
VCC
D3
R17,
1.7k
VCCO
L1
C2
C1
1
2
3
4
56
7
8
9
10
VCC
SW DIP-8
S2
VCC
R47,
130
VEE
VCC
R48,
20
VEE
L7
C18
C17
VEE:
PIN
59
R4,
5k
R3,
5k
R2,
5k
R1,
5k
R23,
5k
R22,
5k
R21,
5k
R20,
5k
R19,
5k
R18,
5k
R1
1,
1.2k
R12,
1.2k
R13,
1.2k
R14,
1.2k
R15,
1.2k
VCC:PIN
24
R16,
5k
JP2
D1
D2
VEE
VCC
5k
VEE:
PIN
56
Notes:
1. C11, C17, C10, C4, C2 = 0.1
F
2. C18, C12, C9, C3, C1 = 1
F
3. C2, C4, C10, C11, and C17 need to be located right at device pin. If vias
to power GND used—use overlapping multiple vias to lower inductance.
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