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參數(shù)資料
| 型號： | SY87813LHG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | AnyRate® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.3Gbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY87813LHGTR SY87813LHGTR-ND |
Micrel, Inc.
SY87813L
November 2006
7
M9999-112806-B
hbwhelp@micrel.com or (408) 955-1690
Functional Block
Functional Description
Clock Recovery
Clock recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the serial data input. The
clock is phase aligned by a PLL so that it samples the
data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency detector. Output
pulses from the detector indicate the required
direction of phase correction. These pulses are
smoothed by a filter. The output of the loop filter
controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered
clock.
Frequency, stability, without incoming data, is
guaranteed by an alternate reference input (REFCLK
or REFCLKP/N) that the PLL locks onto when data is
lost. If the frequency of the incoming signal varies by
greater than approximately 900ppm with respect to
the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference
clock.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal.
Lock Detect
The SY87813L contains a link fault indication circuit,
which monitors the integrity of the serial data inputs. If
the recovered serial data from RDIN is at the correct
data rate (within 900ppm of the synthesizer
frequency), the Link Fault Indicator (LFIN) output will
then be asserted HIGH indicating an in-lock condition
and will remain HIGH as long as this condition is met.
In the event that the recovered serial data is not at the
correct data rate (greater than 900ppm difference
from the synthesizer frequency), then LFIN output will
go LOW indicating an out-of-lock condition. This
condition will force the Clock and Data Recovery PLL
(CDR) to lock onto the synthesizer frequency until it is
within the correct frequency range (less than 900ppm
difference from the synthesizer frequency). Once the
CDR is within the correct frequency range, it will again
lock onto the RDIN input.
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