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參數(shù)資料
| 型號： | SY87813LHG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-TQFP |
| 標準包裝： | 1,000 |
| 系列： | AnyRate® |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.3Gbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY87813LHGTR SY87813LHGTR-ND |
Micrel, Inc.
SY87813L
November 2006
13
M9999-112806-B
hbwhelp@micrel.com or (408) 955-1690
Appendix A
Layout and General Suggestions
1.
Establish controlled impedance stripline, microstrip, or
coplanar construction techniques.
2.
Signal paths should have approximately the same width
as the device pads.
3.
All differential paths are critical timing paths, where
skew should be matched to within ±10ps.
4.
Signal trace impedance should not vary more than
±5%. If in doubt, perform TDR analysis of all high-speed
signal traces.
5.
Maintain compact filter networks as close to filter pins
as possible. Provide ground plane relief under filter path
to reduce stray capacitance. Be careful of crosstalk
coupling into the filter network.
6.
Maintain low jitter on the REFCLK input. Isolate the
XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and
minimize capacitive coupling from adjacent signals.
7.
Higher speed operation may require use of
fundamental-tone (third-overtone typically has more
jitter) crystal-based oscillator for optimum performance.
Evaluate and compare candidates by measuring
TXCLK jitter.
8.
All unused outputs must be terminated. To conserve
power, unused PECL outputs can be terminated with a
1k resistor to VEE.
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