參數(shù)資料
型號: SY89113UMY
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89113 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44
封裝: 7 X 7 MM, LEAD FREE, MO-220, MLF-44
文件頁數(shù): 12/14頁
文件大?。?/td> 522K
代理商: SY89113UMY
Micrel, Inc.
SY89113U
December 2007
M9999-120607
hbwhelp@micrel.com or (408) 955-1690
7
AC Electrical Characteristics
(8)
VCC = +2.5V ±5%; TA = –40°C to + 85°C, RL = 100
across the output pair, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
VOUT
≥ 200mV
1
GHz
tPD
Propagation Delay
CLK0-to-Q
CLK1-to-Q
CLK_SEL-to-Q
VIN
≥ 100mV
625
750
975
ps
VIN
≥ 200mV
700
900
1200
ps
500
700
900
ps
tPD
Tempco
Differential Propagation Delay Temperature
Coefficient
90
fs/
oC
tS
Set-up Time
EN-to-CLK0
EN-to-CLK1
Note 9
100
ps
Note 9
0
ps
tH
Hold Time
CLK0-to-EN
CLK1-to-EN
Note 9
500
ps
Note 9
600
ps
tSKEW
Output-to-Output Skew
Note 10
25
ps
Part-to-Part Skew CLK0
Part-to-Part Skew CLK1
Note 11
200
ps
Note 11
250
ps
tJITTER
Cycle-to-Cycle Jitter
Note 12
1
psRMS
Random Jitter (RJ)
Note 13
1
psRMS
Total Jitter (TJ)
Note 14
10
psPP
Adjacent Channel Crosstalk-induced Jitter
Note 15
0.7
psRMS
tr, tf
Output Rise/Fall Time (20% to 80%)
At full output swing.
80
150
250
ps
Notes:
8.
High-frequency AC-parameters are guaranteed by design and characterization.
9.
Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
10. Output-to-output skew is measured between two different outputs under identical input transitions.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs
12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
13. Random jitter is measured with a K28.7 character pattern, measured at <fMAX.
14. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
15. Crosstalk-induced jitter is defined as: the added jitter that results from signals applied to two adjacent channels. It is measured at the output
while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs.
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