參數(shù)資料
型號: SY89113UMY
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89113 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44
封裝: 7 X 7 MM, LEAD FREE, MO-220, MLF-44
文件頁數(shù): 9/14頁
文件大?。?/td> 522K
代理商: SY89113UMY
Micrel, Inc.
SY89113U
December 2007
M9999-120607
hbwhelp@micrel.com or (408) 955-1690
4
Pin Description
Pin Number
Pin Name
Pin Function
1, 6, 11, 22, 34
GND,
Exposed Pad
Ground. GND pins and exposed pad must both be connected to the most negative
potential of chip the ground.
2, 5
CLK0, /CLK0
Differential Inputs: This input pair is a differential signal input to the device. Input
accepts AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of the
pair internally terminates to a VT pin through 50
. Note that this input defaults to an
indeterminate state if left open. Please refer to the "CLK0 Input Interface
Applications" section for more details.
3
VT0
Input Termination Center-Tap: Each side of the differential input pair CLK0, /CLK0
terminates to the VT pin. The VT pin provides a center-tap to a termination network
for maximum interface flexibility. See “CLK0 Input Interface Applications” section for
more details. For DC-coupled CML or LVDS inputs, the VT pin is left floating.
4
VREF-AC0
Reference Voltage: This output biases to VCC–1.2V. It is used when AC-coupling the
input CLK0. For AC-coupled applications, connect VREF-AC0 to the VT0 pin and
bypass with 0.01F low ESR capacitor to VCC. See “CLK0 Input Interface
Applications” section for more details. Maximum sink/source current is ±1.5mA. Due
to the limited drive capability, the VREF-AC0 pin is only intended to drive its
respective input pin.
7
SE-TERM
Input Termination Pin: When CLK1 is driven by a single-ended TTL/CMOS signal, tie
this pin to GND. In all other modes, let this pin float. See “CLK1 Interface
Applications” section for more details.
8, 10
CLK1, /CLK1
Differential Inputs: This input pair is a differential signal input to the device. This input
accepts Any-Logic standard as small as 200mV (400mVPP). Note that this input
defaults to an indeterminate state if left open. Tie either the true or the complement
input to ground while the other input is floating. This input can be used for single-
ended signals (including TTL/CMOS signals from a 3.3V driver). See “CLK1 Input
Interface Applications” section for more details.
9
VBB1
Reference Voltage: This output biases to VCC–1.425V. VBB1 is designed to act as a
switching reference for the CLK1 and /CLK1 inputs when configured in single-ended
PECL input mode. VBB1 can be used for AC-coupling of CLK1, see Figure 4d for
details. Maximum sink/source current is ±1.5mA. Due to the limited drive capability,
the VBB1 pin is only intended to drive its respective input pin.
12
EN
This single-ended, TTL/CMOS-compatible input functions as a synchronous output
enable. The synchronous enable ensures that enable/disable will only occur when
the outputs are in a logic LOW state. Note that this input is internally connected to a
25k
pull-up resistor and will default to logic HIGH state (enable) if left open.
13, 23, 28,
33, 43
VCC
Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors and place as
close to the VCC pins as possible.
44
CLK_SEL
This single-ended, TTL/CMOS-compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25k
pull-up resistor and will default
to logic HIGH state if open.
42, 41
40, 39
38, 37
36, 35
32, 31
30, 29
27, 26
25, 24
21, 20
19, 18
17, 16
15, 14
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Q10, /Q10
Q11, /Q11
Differential LVDS Outputs: These LVDS output pairs are the precision, low skew
copies of the selected input. Please refer to the, “Truth Table” below for details.
Unused output pairs should be terminated with 100
across the pair. Each output is
designed to drive 325mV into 100
. See the “LVDS Output Interface Applications”
section for more details.
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