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參數(shù)資料
| 型號： | SY89297UMG |
| 廠商： | MICREL INC |
| 元件分類： | 延遲線 |
| 英文描述： | ACTIVE DELAY LINE, QCC24 |
| 封裝： | 4 X 4 MM, LEAD FREE, QFN-24 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 572K |
| 代理商： | SY89297UMG |
Micrel, Inc.
SY89297U
February 2009
7
M9999-022509-C
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
(7)
TA = -40°C to +85°C, Channels A & B, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
Clock: Vout Swing >200mVpk
1.6
GHz
NRZ Data
3.2
Gbps
tpd
Propagation Delay
IN to Q; D[0–9]=0
IN to Q; D[0–9]=1023
/EN to Q: D[0–9]=0; VTH = VCC/2
SDATA to SOUT (D0–D9=Low),
No load
1000
5500
1000
2000
7500
2500
4500
ps
tRANGE
Programmable Range
tpd (max) – tpd (min)
4150
5115
ps
tSKEW
Duty Cycle Skew
tPHL – tPLH
Note 8
45
55
%
t
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
D0-D9 High
5
10
20
40
80
160
320
640
1280
2560
5115
ps
Monotonic
-5
25
ps
INL
Integral Non-Linearity
Note 9
15
+15
ps
tS
Setup Time
SDATA to SCLK
SCLK to SLOAD
/EN to IN
Note 10
Note 11
400
300
ps
tH
Hold Time
SLOAD to SCLK
IN to /EN
SCLK to SDATA
Note 12
Note 13
300
100
200
ps
tPW
Pulse Width
SLOAD
1000
ps
tR
Release Time
/EN to IN
Note 14
800
ps
tJITTER
Cycle-to-Cycle Jitter
Total Jitter
Random Jitter
Note 15
Note 16
Note 17
2
20
2
psRMS
psPP
psRMS
tr, tf
Output Rise/Fall Time
20% to 80% (Q)
30
55
80
ps
Duty Cycle
Input Frequency = 1.6GHz
45
55
%
Notes:
7.
High frequency AC electricals are guaranteed by design and characterization.
8.
Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output.
9.
INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The
maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1023. INL = measured
delay – (measured minimum delay + (step number x TIL)).
10. SCLK has to transition L-H a setup time before the SLOAD H-L transition to ensure the valid data is properly latched. See timing diagram "Setup
and Hold Time: SCLK and SLOAD.”
11. This setup time is the minimum time that /EN must be asserted prior to the next transition of IN / /IN to prevent an output response greater than +
75 mV to that IN or /IN transition. See timing diagram Setup, Hold and Release Time: IN and /EN."
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相關代理商/技術參數(shù) |
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|---|---|
| SY89297UMG TR | 功能描述:延遲線/計時元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89297UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMH | 功能描述:延遲線/計時元素 2.5V Dual Channel Delay Line with 5ps Step Delay (improved SY89295) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89297UMH TR | 功能描述:延遲線/計時元素 2.5V Dual Channel Delay Line with 5ps Step Delay (improved SY89295) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89306 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V/5V 2.5GHz PECL/ECL DIFFERENTIAL RECEIVER/BUFFER |
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