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參數(shù)資料
| 型號： | SY89297UMG |
| 廠商： | MICREL INC |
| 元件分類： | 延遲線 |
| 英文描述： | ACTIVE DELAY LINE, QCC24 |
| 封裝： | 4 X 4 MM, LEAD FREE, QFN-24 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大小： | 572K |
| 代理商： | SY89297UMG |
Micrel, Inc.
SY89297U
February 2009
8
M9999-022509-C
hbwhelp@micrel.com or (408) 955-1690
12. SCLK has to transition L-H a hold time after the SLOAD H-L transition to ensure that the valid data is properly latched before starting to load new
data. See timing diagram "Setup and Hold Time: SCLK and SLOAD.”
13. This hold time is the minimum time that /EN must remain asserted after a negative going transition of IN to prevent an output response greater than
+75mv to the IN transition. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
14. This release time is the minimum time that /EN must be de-asserted prior to the next IN / /IN transition to affect the propagation delay of IN to Q
less than 1ps. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
15. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs.
Tjitter_cc = Tn – Tn+1, where T is the time between rising edges of the output signal.
16. Total jitter definition: With an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-
peak jitter value.
17. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean.
Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.
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| SY89464UMYTR | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| SY89464UMY | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| SY89467UHYTR | 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| SY89467UHY | 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| SY89482LMG | LOW SKEW CLOCK DRIVER, QCC24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89297UMG TR | 功能描述:延遲線/計時元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89297UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMH | 功能描述:延遲線/計時元素 2.5V Dual Channel Delay Line with 5ps Step Delay (improved SY89295) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89297UMH TR | 功能描述:延遲線/計時元素 2.5V Dual Channel Delay Line with 5ps Step Delay (improved SY89295) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89306 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V/5V 2.5GHz PECL/ECL DIFFERENTIAL RECEIVER/BUFFER |
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