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參數(shù)資料
| 型號(hào)： | SY89536LHZ |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 89536 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 101K |
| 代理商： | SY89536LHZ |
9
Precision Edge
SY89536L
Micrel, Inc.
M9999-010808
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
At the core of the SY89536L clock synthesizer is a
precision PLL driven by a differential or single-ended
reference input. For users who wish to supply a crystal
input, please use the SY89531L. The PLL output is sent to
three banks of outputs. Each bank has its own programmable
frequency divider, and the design is optimized to provide
very low skew between banks, and very low jitter.
PLL Programming and Operation
IMPORTANT: If the internal VCO will be used, VCO_SEL
must be tied LOW, and ExtVCO pins can be left
unconnected. The internal VCO range is 600MHz to
1000MHz, and the feedback ratio is selectable via the MSEL
divider control (M3:0 pins). The feedback ratio can be
changed without powering the chip down. The PLL output
is fed to three banks of outputs: Bank A, Bank B, and Bank
C. Banks A and C each have two differential LVPECL output
pairs. Bank B has nine differential HSTL output pairs.
Each bank has a separate frequency divider circuit that
can be reprogrammed on the fly. The FSEL_x0:2 (where x
is A, B, or C) pins control the divider value. The FSEL
divider can be programmed in ratios from 2 to 18, and the
outputs of Banks A, B, and C can be synchronized after
programming by pulsing the OUT_SYNC pin HIGH-LOW-
HIGH. Setting a value of 000 for FSEL is an output disable
forcing the Q outputs to be LOW and the /Q outputs to be
HIGH. Doing so will decrease power consumption by
approximately 5mA per bank.
To determine the correct settings for SY89536L follow
these steps:
1. Refer to the
“Suggested Selections for Specific
Customer Applications” section for common applications,
as well as the formula used to compute the output frequency.
2. Determine the desired output frequency, such as
66MHz.
3. Choose a reference input frequency between 14MHz
and 20MHz. The user can also choose a higher input
frequency, and use the PSEL pre-divider to divide it down
to the 14MHz to 20MHz range. In this example, we choose
18MHz for the reference input frequency. This results in an
input/output ratio of 66/18.
4. Refer to the
“Feedback Divide Select” table and the
“Post-Divide Frequency Select” table to find values for MSEL
and FSEL such that MSEL/FSEL equals the same 66/18
ratio. In this example, values of MSEL=44 and FSEL=12
work.
5. Make sure that REFCLK
÷ PSEL × MSEL is between
600MHz and 1000MHz.
The user may need to experiment with different REFCLK
input frequencies to satisfy these requirements.
470pF
Loop
Filter
Loop
Reference
330
0.2
F
Figure 1. External Loop Filter Connection
External Loop Filter Considerations
The SY89536L features an external PLL loop filter that
allows the user to tailor the PLL’s behavior to their application
and operating environment. We recommend using ceramic
capacitors with NPO or X7R dielectric, as they have very
low effective series resistance. For applications that require
ultra-low cycle-to-cycle jitter, use the components shown in
Figure 1. The PLL loop bandwidth is a function of feedback
divider ratio, and the external loop filter allows the user to
compensate. For instance, the PLL’s loop bandwidth can
be decreased by using a smaller resistor in the loop filter.
This results in less noise from the PLL input, but potentially
more noise from the VCO. Refer to
“AC Electrical
Characteristics” for target PLL loop bandwidth. The designer
should take care to keep the loop filter components on the
same side of the board and as close as possible to the
SY89536L’s LOOP_REF and LOOP_FILTER pins. To insure
minimal noise pick-up on the loop filter, it is desirable to cut
away the ground plane directly underneath the loop filter
component pads and traces. However, the benefit may not
be significant in all applications and one must be careful to
not alter the characteristic impedance of nearby traces.
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power supply
filtering is very important. At a minimum, V
CCA, VCC_Logic,
and all V
CCO pins should be individually connected using a
via to the power supply plane, and separate bypass
capacitors should be used for each pin. To achieve optimal
jitter performance, each power supply pin should use
separate instances of the circuit shown in Figure 2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89536LHZ TR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V Programmable HSTL/LVPECL Synthesizer (Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89536LHZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89537L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89537L_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89537LMG | 功能描述:IC SYNTHESIZR LVPECL/LVDS 44-MLF RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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