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參數(shù)資料
| 型號： | SY89536LHZ |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89536 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 101K |
| 代理商： | SY89536LHZ |
10
Precision Edge
SY89536L
Micrel, Inc.
M9999-010808
hbwhelp@micrel.com or (408) 955-1690
*For VCC_Analog,VCC_TTL, VCC1,
use ferrite bead = 200mA, 0.45
DC,
Murata P/N BLM21A1025
*For VCCOA,B,C use ferrite bead = 3A, 0.025
DC,
Murata, P/N BLM31P005
*Component size: 0805
1
F
22
F
0.01
F
Ferrite Bead*
Power Supply
side
Device
side
VCC
Pins
Figure 2. Power Supply Filtering
Output Logic Characteristics
See
“Output Termination Recommendations” for
illustrations. In cases where single-ended output is desired,
the designer should terminate the unused complimentary
output in the same manner as the normal output that is
being used. Unused output pairs can be left floating.
LVPECL operation:
Typical voltage swing is 700mV
PP to 800mVPP into
50
.
Common mode voltage is V
CC–1.3V, typical.
100
termination across the output pair is NOT
recommended for LVPECL. See
“Output Termination”
section, Figures 5 to 7.
HSTL operation (Bank B):
Typical voltage swing is 250mV
PP to 450mVPP into
effective 50
.
Thermal Considerations
This part has an exposed die pad for enhanced heat
dissipation. We strongly recommend soldering the exposed
die pad to a ground plane. Where this is not possible, we
recommend maintaining at least 500lfpm air flow around
the part.
For additional information on exposed-pad characteristics
and implementation details, see Amkor Technology’s web
site, www.amkor.com.
REFCLK Input Interface
The flexible REFCLK inputs are designed to accept any
differential or single-ended input signal within 300mV above
VCC and 300mV below ground.
Do not leave unused REFCLK inputs floating. Tie either
the true or complement inputs to ground, but not both. A
logic zero is achieved by connecting the complement input
to ground with the true input floating. For a TTL input, tie a
resistor between the complement input and ground. See
“Input Interface” section, Figures 4a through 4h.
Input Levels
LVDS, CML and HSTL differential signals may be
connected directly to the REFCLK inputs. Depending on
the actual worst case voltage seen, the minimum input
voltage swing varies.
R2
990
R2
990
R1
825
R1
825
GND
REFCLK
VCC
/REFCLK
Figure 3. Simplified Input Structure
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89536LHZ TR | 功能描述:時鐘合成器/抖動清除器 3.3V Programmable HSTL/LVPECL Synthesizer (Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89536LHZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89537L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89537L_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89537LMG | 功能描述:IC SYNTHESIZR LVPECL/LVDS 44-MLF RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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