參數(shù)資料
型號(hào): SY89537LMHTR
廠商: MICREL INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 756 MHz, OTHER CLOCK GENERATOR, QCC44
封裝: 7 X 7 MM, LEAD FREE, MO-220, MLF-44
文件頁(yè)數(shù): 7/19頁(yè)
文件大?。?/td> 819K
代理商: SY89537LMHTR
Micrel, Inc.
SY89537L
July 2005
M9999-072105
hbwhelp@micrel.com or (408) 955-1690
15
Figure 6 shows the open and closed loop gain of the
SY89537L. The closed loop-gain plot shows that the
SY89537L when configured with the recommended
loop filter values has essentially no jitter peaking near
the -3dB point. In addition, the open loop curve shows
the frequency at which unity gain occurs for a typical
case of the SY89537L with VCC = 3.3V at TA = 25°C.
At unity gain, Figure 7 can be used to determine the
phase margin or stability of the SY89537L.
Figure 6. Open and Closed Loop Gain
at VCC = 3.3V, TA = 25°C
Figure 7. Phase Margin Plot
at VCC = 3.3V, TA = 25°C
Figure 8 illustrates the VCO frequency versus the loop
filter control voltage at 3.3V, TA = 25°C. The normal
loop filter control voltage is -300mV to +300mV.
Figure 9 illustrates the VCO gain curve at VCC = 3.3V,
TA = 25°C. With this set of information, determining
the loop stability with other sets of loop filter
configurations are possible.
Figure 8. VCO Frequency vs.
Loop Filter Control Voltage at 3.3V, TA = 25°C
Figure 9. VCO Gain vs.
Loop Filter Control Voltage at 3.3V, TA = 25°C
Input Interface
RFCK is designed to accept any differential or single-
ended input signal 300mV above VCC or 300mV below
GND. RFCK should not be left floating. Tie either the
true or complement input to GND, but not both. A logic
zero is achieved by connecting the complement input
to GND with the true input floating. For TTL input, tie a
2.5k resistor between the complement input and
GND. LVDS, CML and HSTL differential signals may
be connected directly to the reference inputs.
Figure 10. Simplified Input Structure
dB
Phase
M
argin
(
°)
Frequency (Hz)
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