參數(shù)資料
型號: SYS8512FKXL-10
英文描述: 512K x 8 SRAM MODULE
中文描述: 為512k × 8的SRAM模塊
文件頁數(shù): 4/7頁
文件大小: 69K
代理商: SYS8512FKXL-10
ISSUE 5.0 November 1999
SYS8512FKX-70/85/10/12
4
Read Cycle
AC OPERATING CONDITIONS
-70
-85
-10
-12
Parameter
Symbol mn
max
mn
max
mn
max
mn
max Unt
Read Cycle Time
t
RC
t
AA
70
-
85
-
100
-
120
-
ns
Address Access Time
-
70
-
85
-
100
-
120
ns
Chip Select Access Time
t
ACS
t
OE
-
70
-
85
-
100
-
120
ns
Output Enable to Output Valid
-
50
-
55
-
60
-
70
ns
Output Hold from Address Change
t
OH
10
-
10
-
10
-
10
-
ns
Chip Selection to Output in Low Z
t
CLZ
t
OLZ
10
-
10
-
10
-
10
-
ns
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
ns
Chip Deselection to O/P in High Z
t
CHZ
t
OHZ
0
25
0
30
0
35
0
45
ns
Output Disable to Output in High Z
0
25
0
30
0
35
0
45
ns
Notes. (1) t
and t
are defined as the time at which the outputs achieve open circuit conditions and are not referenced
to output voltage levels.These parameters are sampled and not 100% tested.
-70
-85
-10
-12
Parameter
Sym
mn
max
mn
max
mn
max
mn
max Unt
Write Cycle Time
t
WC
70
-
85
-
100
-
120
-
ns
Chip Selection to End of Write
t
CW
t
AW
60
-
80
-
90
-
100
-
ns
Address Valid to End of Write
60
-
80
-
90
-
100
-
ns
Address Setup Time
t
AS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
t
WR
55
-
65
-
75
-
85
-
ns
Write Recovery Time
5
-
5
-
10
-
10
-
ns
Write to Output in High Z
t
WHZ
t
DW
(11)
0
25
0
30
0
35
0
40
ns
Data to Write Time Overlap
30
-
35
-
40
-
45
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
0
-
ns
Output active from end of write
t
OW
(10)
5
-
5
-
5
-
5
-
ns
Write Cycle
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SYS8512FKXLI-12 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 SRAM MODULE