參數(shù)資料
型號: T4260
廠商: Atmel Corp.
英文描述: AM/FM Front End IC
中文描述: 調(diào)幅/調(diào)頻前端IC
文件頁數(shù): 20/31頁
文件大?。?/td> 299K
代理商: T4260
20
T4260
4528G–AUDR–12/03
DAC1, 2 (Pins 1, 2)
For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by set-
ting gain and offset values. The principle of the operation is shown in Figure 7. The gain
is in the range of 0.67
×
V
Tune
to 2.09
×
V
Tune
. The offset range is +0.98 V to -0.98 V.
For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filter
and the IF filter. For alignment, offset and gain are set for having the best tuner tracking.
Figure 7.
Block Diagram of DAC1, 2
The gain of DAC1 and DAC2 has a range of approximately 0.67
×
V(VTUNE) to
2.09
×
V(TUNE). This range is divided into 255 steps. One step is approximately (2.09-
0.67)/255 = 0.00557
×
V(TUNE). The gain of DAC1 can be controlled by the Bits 38 to
45 (2
0
to 2
7
) and the gain of DAC2 can be controlled by the Bits 66 to Bit 73 (2
0
to 2
7
) as
given in Table 26.
Table 26.
Gain of DAC1, 2
Gain DAC1
Approximately
Gain DAC2
Approximately
0.6728
×
V(TUNE)
0.6783
×
V(TUNE)
0.6838
×
V(TUNE)
0.6894
×
V(TUNE)
...
0.9959
×
V(TUNE)
...
2.0821
×
V(TUNE)
2.0877
×
V(TUNE)
2.0932
×
V(TUNE)
Offset = 64 (intermediate position)
The offset of DAC1 and DAC2 has a range of approximately +0.98 V to -0.99 V. This
range is divided into 127 steps. One step is approximately 1.97 V/127 = 15.52 mV. The
offset of DAC1 can be controlled by the Bits 24 to Bit 30 (2
0
to 2
6
) and the offset gain of
DAC2 can be controlled by the Bits 52 to Bit 58 (2
0
to 2
6
) as given in Table 27.
B45
B44
B43
B42
B41
B40
B39
B38
Decimal
Gain
Decimal
Gain
0
1
2
3
...
58
...
253
254
255
B73
0
0
0
0
...
0
...
1
1
1
B72
0
0
0
0
...
0
...
1
1
1
B71
0
0
0
0
...
1
...
1
1
1
B70
0
0
0
0
...
1
...
1
1
1
B69
0
0
0
0
...
1
...
1
1
1
B68
0
0
0
0
...
0
...
1
1
1
B67
0
0
1
1
...
1
...
0
1
1
B66
0
1
0
1
...
0
...
1
0
1
VTUNE
Offset
Gain
DAC1, 2
+/-
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