參數(shù)資料
型號: T4260
廠商: Atmel Corp.
英文描述: AM/FM Front End IC
中文描述: 調(diào)幅/調(diào)頻前端IC
文件頁數(shù): 24/31頁
文件大小: 299K
代理商: T4260
24
T4260
4528G–AUDR–12/03
Figure 11.
Block Diagram of the PLL Core
PLL Core Block Diagram
Description
The two N-dividers are stored in two 18-bit memory register (LATCH N-DIV) and the
R-divider in a 14-bit memory register (LATCH R-DIV). One of the the two N-dividers
(N1 or N2) can be activated by Bit 5 as active N-divider (with the 18-bit multiplexer
MUX).
The (divider) 2-bit shift mode can be activated with Bit 32 = 0. The N- and R-divider are
shifted two bits to the right in this shift mode. Because the two lowest R-divider bits
(Bit 124 and Bit 125) are 0 they do not have to be evaluated. In opposite to the R-divider
the lowest two N-divider bits (Bit 102 and Bit 103 or Bit 80 and Bit 81, depends on the
active N-divider) are special evaluated in the ACCU block if fractional mode is active
(Bit 144 = 0). The two lowest N- and R-divider bits are also called shift bits.
The SWITCH N+1, N block is steering the division through N or N+1 in the N-divider if
fractional and 2-bit shift mode are active. There is only a division by N if the fractional
mode is deactivated in 2-bit shift mode.
The output signals of the 18-bit N-divider and 14-bit R-divider will be compared in the
PHASEDETECTOR which one activates the sink and source currents of the charge
pumps (CP).
LATCH R - DIV.
SHIFT 2 BIT
R - DIVIDER
DELAYTIME high
cur. CP
SWITCH
PHASE
DETECTOR
CHARGE
PUMP
AM/FM
FILTER
N / N+1
DIVIDER
PREAMP
SWITCH N+1, N
ACCU 2 - BIT
SHIFT 2 BIT
MUX N1 N2
LATCH N - DIV 1
LATCH N - DIV 2
VCO
FM - LOOP
FILTER
AM - LOOP
FILTER
B60, B144
2-BIT (LSB)
18 - BIT
18 - BIT
BIT 18
BIT 32
Fref
14 - BIT
B145
AM / FM
HCDEL 1 HCDEL 2
B62,63
B61
B5
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