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參數(shù)資料
| 型號： | T436416A-7.5SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 4M X 16 SDRAM |
| 中文描述： | 4米× 16內存 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 712K |
| 代理商： | T436416A-7.5SG |
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TE
CH
tm
Burst Read Single bit Write Cycle @ Burst Length = 2
0
1
2
3
4
T436416A
TM Technology Inc. reserves the right
P.25
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
C L = 2
C L = 3
W E
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H IG H
D Q M
D Q
:D o n 't c a re
* N o te2
R A a
C A a
R B b
C A b
R A c
C B c
C A d
R A a
R B b
R A c
D A a0
D A a0
D A b 0
D A b 0
D A b 1
D A b 1
D B c0
D B c0
D A d 0
D A d 1
D A d 0
D A d 1
R o w A c tiv e
(A -B a n k )
W rite (A -
B an k )
R o w A c tiv e
(A -B a n k )
R ead w ith A u to
P rech arg e (A -
B an k )
R o w A c tiv e
(A -B a n k )
W rite w ith A u to
P rech arg e (A -
B an k )
R ead (A -
B an k )
P rech arg e
(A -B a n k )
*Note : 1. BRSW modes is enabled by setting A
9
‘High’ at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to ‘1’ regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that
t
RAS
should not
be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command,
the precharge command will be issued after two clock cycle.
相關PDF資料 |
PDF描述 |
|---|---|
| T436416A-7S | TERMINAL BLOCK END BARRIER IEC +OPTIONS |
| T436416A-7SG | 4M X 16 SDRAM |
| T436416A-8S | 4M X 16 SDRAM |
| T436416A-8SG | 4M X 16 SDRAM |
| T436416C | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T436416A-7S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-8S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-8SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416C | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
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