參數(shù)資料
型號: T436416A-7S
廠商: TM Technology, Inc.
英文描述: TERMINAL BLOCK END BARRIER IEC +OPTIONS
中文描述: 4米× 16內(nèi)存
文件頁數(shù): 7/29頁
文件大?。?/td> 712K
代理商: T436416A-7S
TE
CH
tm
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
T436416A
TM Technology Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
Speed Version
-7
-7.5
14
15
Parameter
Symbol
-6
12
-8
16
-10
20
Unit
Note
Row active to row active delay
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
ns
1
RAS to CAS delay
16
18
18
20
20
ns
1
Row precharge time
18
20
20
20
20
ns
1
42
42
45
100K
65
1
48
50
ns
ns
ns
CLK
1
1
2
Row active time
Row cycle time
Last data in to new col. Address delay
t
CDL
(min)
Last data in to row precharge
60
63
68
70
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
2
CLK
2
Last data in to burst stop
1
CLK
2
Col. Address to col. Address delay
1
1
1
CLK
3
Number of valid output data
ea
4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
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