參數(shù)資料
型號(hào): T436416C-6SG
廠商: TM Technology, Inc.
英文描述: 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
中文描述: 4米× 16 SDRAM的100萬(wàn)x 16Bit的X 4Banks同步DRAM
文件頁(yè)數(shù): 16/28頁(yè)
文件大?。?/td> 651K
代理商: T436416C-6SG
TE
CH
tm
Read & Write Cycle at Same Bank @Burst Length = 4
0
1
2
3
4
T436416C
TM Technology Inc. reserves the right
P.16
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
C L O C K
C K E
C S
R A S
C A S
A D D R
A 1 3 ,A 1 2
A 1 0 /A P
C L = 2
C L = 3
W E
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H IG H
t
R C
D Q M
D Q
:D o n 't care
* N o te 1
t
R C D
* N o te 2
* N o te 4
* N o te 3
* N o te 3
* N o te 4
R a
C a0
R b
C b 0
R b
R a
Q a0
Q a1
Q a2
Q a3
Q a0
Q a1
Q a2
Q a3
D b 0
D b 0
D b 1
D b 1
D b 2
D b 2
D b 3
D b 3
t
R A C
t
S A C
t
O H
t
O H
t
S A C
t
S H Z
t
S H Z
t
R D L
t
R D L
R ow
A ctive (A -
B an k )
R ead (A -
B an k )
P recharg
e (A -
B an k )
R ow A ctive
(A -B n ak )
W rite (A -
B n ak )
P recharge
(a-B n ak )
*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z(
t
SHZ
) after the clock.
3. Access time from Row active command.
t
CC
*(
t
RCD
+CAS latency-1)+
t
SAC
4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T436416C-7S 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
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T436416D-5C 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
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