參數(shù)資料
型號: T436416D-6CG
廠商: TM Technology, Inc.
英文描述: 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM
中文描述: 4米× 16 SDRAM的100萬x 16Bit的X 4Banks同步DRAM
文件頁數(shù): 8/73頁
文件大小: 734K
代理商: T436416D-6CG
TE
CH
tm
T436416D
TM Technology Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
CLK
DQM
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
ABANKA
DIN A0
DIN A1
DIN A2
DIN A3
1 Clk Interval
CAS# latency=2
tCK2, DQ's
: "H" or "L"
READ A
WRITE A
Read to Write Interval
(Burst Length
4, CAS# Latency = 2)
CLK
DQM
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
READ A
NOP
WRITE B
NOP
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B3
CAS# latency=2
tCK2, DQ's
: "H" or "L"
NOP
NOP
Read to Write Interval
(Burst Length
4, CAS# Latency = 2)
command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll
command is issued in different CAS# latency.
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll
CLK
COMMAND
CAS# latency=2
tCK2, DQ's
T0
T 1
T2
T3
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP
NOP
Activate
NOP
NOP
Precharge
CAS# latency=3
tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
ADDRESS
t
RP
Bank,
Col A
Bank(s)
Bank,
Row
Read to Precharge
(CAS# Latency = 2, 3)
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