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參數(shù)資料
| 型號： | T436416D-7S |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 4米× 16 SDRAM的100萬x 16Bit的X 4Banks同步DRAM |
| 文件頁數(shù)： | 18/73頁 |
| 文件大?。?/td> | 734K |
| 代理商： | T436416D-7S |
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TE
CH
tm
Electrical Characteristics and Recommended A.C. Operating Conditions
(V
DD
= 3.3V
±
0.3V, T
A
= 0~70
°
C) (Note: 5, 6, 7, 8)
T436416D
TM Technology Inc. reserves the right
P. 18
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
-
5/6/7
Symbol
t
RC
A.C. Parameter
Min.
Max.
Unit
Note
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command (same
bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time
50/60/63
t
RCD
15/18/20
t
RP
15/18/20
ns
t
RRD
10/12/14
t
RAS
35/42/45
t
WR
2
t
CCD
t
CK2
t
CK3
CAS# to CAS# Delay time
1
CLK
CL* = 2
10/10/10
9
Clock cycle time
CL* = 3
5/6/7
t
CH
Clock high time
2/2.5/2.5
10
t
CL
Clock low time
2/2.5/2.5
10
t
AC2
CL* = 2
6/6/6
10
t
AC3
Access time from CLK
(positive edge)
CL* = 3
4.5/5/5.4
ns
t
OH
t
LZ
Data output hold time
2/2.5/2.7
9
Data output low impedance
1
t
HZ
Data output high impedance
4.5/5/5.4
8
t
IS
Data/Address/Control Input set-up time
1.5/1.5/1.5
10
t
IH
Data/Address/Control Input hold time
1
10
t
PDE
Power Down Exit set-up time
1.5/1.5/1.5
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2. All voltages are referenced to V
SS
.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of t
CK
and t
RC
. Input signals are changed one time during t
CK
.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T436416D-7SG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436432B-5S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-5SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-6S | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-6SG | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T436416D-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436432B | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10S | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-10SG | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| T436432B-55S | 制造商:TMT 制造商全稱:TMT 功能描述:2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
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