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參數(shù)資料
| 型號： | T436432B-10SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM |
| 中文描述： | 200萬× 32內存為512k × 32 x 4Banks同步DRAM |
| 文件頁數(shù)： | 18/72頁 |
| 文件大小： | 731K |
| 代理商： | T436432B-10SG |
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TE
CH
tm
Electrical Characteristics and Recommended A.C. Operating Conditions
(V
DD
= 3.3V
±
0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
T436432B
TM Technology Inc. reserves the right
P. 18
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
- 5/5.5/6/7/8/10
Min.
Symbol
t
RC
A.C. Parameter
Max.
Unit Note
Row cycle time
(same bank)
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command (same
bank)
Row activate to precharge time
(same bank)
Clock cycle time
55/55/60/70/80/100
9
t
RRD
10/11/12/14/16/20
9
t
RCD
18/18/18/21/24/30
9
t
RP
15/16.5/18/21/24/30
9
t
RAS
35/38.5/42/49/56/70
100,000
9
t
CK2
t
CK3
CL* = 2
-/-/10/10/ - / -
CL* = 3
5/5.5/6/7/8/10
ns
t
AC2
Access time from CLK
CL* = 2
-/-/6/6/-/-
9
t
AC3
(positive edge)
CL* = 3
4.5/5/5.5/5.5/6/6
t
OH
Data output hold time
2/2/2/2.5/2.5/2.5
9
t
CH
Clock high time
2/2/2.5/3/3/3.5
10
t
CL
Clock low time
2/2/2.5/3/3/3.5
10
t
IS
Data/Address/Control Input set-up time
1.5/1.5/1.5/1.75/2/2.5
10
t
IH
Data/Address/Control Input hold time
1
10
t
LZ
Data output low impedance
1
9
t
HZ2
Data output high impedance
CL* = 2
-/-/6/6/-/-
t
HZ3
CL* = 3
4.5/5/5.5/5.5/6/6
8
t
WR
Write recovery time
2
t
CCD
CAS# to CAS# Delay time
2/1/1/1/1/1
CLK
t
MRS
Mode Register Set cycle time
2
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2. All voltages are referenced to V
SS
. VIL(Max) = VDDQ+1.0V for pulse width < 2ns. VIL(Min) = -1.0V for pulse
width < 2.0ns
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value
of t
CK
and t
RC
. Input signals are changed one time during t
CK
.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
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