參數(shù)資料
型號(hào): T436432B-6SG
廠商: TM Technology, Inc.
英文描述: 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM
中文描述: 200萬× 32內(nèi)存為512k × 32 x 4Banks同步DRAM
文件頁數(shù): 4/72頁
文件大?。?/td> 731K
代理商: T436432B-6SG
TE
CH
tm
PIN DESCRIPTION
T436432B
TM Technology Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all input.
CS
Chip Select
Disables or enables device operation by masking or enabling all input
except CLK,CKE and DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Auot-precharge flag : A10/AP
BS0~1
Bank Select Address
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK
with
RAS
low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK
with
CAS
low.
Enables column access .
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
DQM0~3
Data Input/Output
Mask
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ DQ31
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power Supply/Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output
Power/Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C
No Connection
No Connection.
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