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| 型號： | T48C893-TK |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | The multiple times programmable (MTP) version for the MARC4 ROM types |
| 中文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 13/82頁 |
| 文件大?。?/td> | 638K |
| 代理商： | T48C893-TK |
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T48C893
Rev. A4, 22-Jan-02
13 (82)
Table 2 Interrupt priority table
Interrupt
INT0
INT1
Priority
lowest
|
ROM Address
040h
080h
Interrupt Opcode
C8h (SCALL 040h)
D0h (SCALL 080h)
Function
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INT4
INT5
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|
|
140h
180h
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E8h (SCALL 140h)
F0h (SCALL 180h)
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Software interrupt (SWI0)
Timer 2 interrupt
Timer 3 interrupt
External hardware interrupt, any edge at BP52
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Table 3 Hardware interrupts
Interrupt
Interrupt Mask
Interrupt Source
Register
Bit
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INT7
VCM
VIM
T3IM1
P51M1, P51M2
External / internal voltage monitoring
any edge at BP51
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Software Interrupts
The programmer can generate interrupts by using the
software interrupt instruction (SWI) which is supported
in qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
hardware triggered interrupt. The SWI instruction takes
the top two elements from the expression stack and writes
the corresponding bits via the I/O bus to the interrupt
pending register. Therefore, by using the SWI instruction,
interrupts can be re-prioritized or lower priority processes
scheduled for later execution.
Hardware Interrupts
In the T48C893, there are eleven hardware interrupt
sources with seven different levels. Each source can be
masked individually by mask bits in the corresponding
control registers. An overview of the possible hardware
configurations is shown in table 4.
3.3
Master Reset
The master reset forces the CPU into a well-defined
condition. It is unmaskable and is activated independent
of the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power sup-
ply, brown-out detection circuitry, watchdog time-out, or
an external input clock supervisor stage (see figure 9). A
master reset activation will reset the interrupt enable flag,
the interrupt pending register and the interrupt active
register. During the power-on reset phase the I/O bus con-
trol signals are set to
’
reset mode
’
thereby initializing all
on-chip peripherals. All bidirectional ports are set to input
mode.
Attention: During any reset phase, the BP20/NTE input
is driven towards V
DD
by a strong pull-up transistor.
Releasing the reset results in a short call instruction
(opcode C1h) to the EEPROM address 008h. This acti-
vates the initialization routine $RESET which in turn has
to initialize all necessary RAM variables, stack pointers
and peripheral configuration registers (see table 7).
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