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參數(shù)資料
| 型號(hào)： | T48C893-TK |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | The multiple times programmable (MTP) version for the MARC4 ROM types |
| 中文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 33/82頁 |
| 文件大?。?/td> | 638K |
| 代理商： | T48C893-TK |
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T48C893
Rev. A4, 22-Jan-02
33 (82)
able and disable the modulator output for a programmable
count of pulses.
For programming the time interval, the timer has a 4-bit
and an 8-bit compare register. For programming the timer
function, it has four mode and control registers. The
comparator output of stage 2 is controlled by a special
compare mode register (T2CM). This register contains
mask bits for the actions (counter reset, output toggle,
timer interrupt) which can be triggered by a compare
match event or the counter overflow. This architecture en-
ables the timer function for various modes.
Timer 2 compare data values
The Timer 2 has a 4-bit compare register (T2CO1) and an
8-bit compare register (T2CO2). Both these compare
registers are cascadable as a 12-bit compare register, or
8-bit compare register and 4-bit compare register.
For 12-bit compare data value:m = x +1 0
≤
x
≤
4095
For 8-bit compare data value: n = y +1 0
≤
y
≤
255
For 4-bit compare data value: l = z +1
0
≤
z
≤
15
4
–
bit Counter 2/1
RES
OVF1
Compare 2/1
T2CO1
CM1
POUT
SSI POUT
CL2/2
DCG
T2M1
P4CR
8
–
bit Counter 2/2
RES
OVF2
Compare 2/2
T2CO2
T2CM
Control
TOG2
INT4
Biphase
–
,
Manchester
–
modulator
OUTPUT
MOUT
M2
to
Modulator 3
T2O
Timer 2
modulator
output
–
stage
T2M2
SO
Control
SSI
SSI
I/O
–
bus
T2C
CL2/1
T2I
SYSCL
T1OUT
TOG3
SCL
I/O
–
bus
13776
DCGO
Figure 30. Timer 2
Timer 2 Modes
Mode 1: 12-bit compare counter
4-bit counter
4-bit compare
RES
4-bit register
CM1
POUT (CL2/1 /16)
8-bit counter
8-bit compare
8-bit register
OVF2
CM2
RES
T2RM
T2OTM
Timer 2
output mode
and T2OTM
–
bit
T2IM
T2CTM
TOG2
INT4
CL2/1
13778
DCG
T2D1, 0
Figure 31. 12-bit compare counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and
the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. The compare action is program-
mable via the compare mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output (POUT)
with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
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