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參數(shù)資料
| 型號： | T5743 |
| 廠商： | Atmel Corp. |
| 英文描述： | UHF ASK/FSK Receiver |
| 中文描述： | 超高頻ASK / FSK接收器 |
| 文件頁數(shù)： | 14/41頁 |
| 文件大?。?/td> | 681K |
| 代理商： | T5743 |
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14
T5743
4569A–RKE–12/02
T
Lim_min
= Lim_min T
XClk
T
Lim_max
= (Lim_max –1) T
XClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the
required T
Lim_min
, T
Lim_max
and T
XClk
. The time resolution defining T
Lim_min
and T
Lim_max
is
T
XClk
. The minimum edge-to-edge time t
ee
(t
DATA_L_min
, t
DATA_H_min
) is defined according
to the section ‘Receiving Mode’. The lower limit should be set to Lim_min 10. The
maximum value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits
(N
Bit-check
) to prevent switching to receiving mode due to noise.
Figure 13, Figure 14 and Figure 15 illustrate the bit check for the bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T
Startup
. The output of the ASK/FSK demodulator (Dem_out) is unde-
fined during that period. When the bit check becomes active, the bit-check counter is
clocked with the cycle T
XClk
.
Figure 13 shows how the bit check proceeds if the bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 14 the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 15.
Figure 13.
Timing Diagram During Bit Check
Figure 14.
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check
IC_ACTIVE
Dem_out
Bit-check-
counter
0
2 3 4 5 6
2
4 5
1
7 8 1
3
6 7 8 9
11 12 13 14
10
1/2 Bit
15 16 17 18 1 2 3 4
5
6
( Lim_min = 14, Lim_max = 24 )
7 8 9 10 11 12 13 14 15 1 2 3 4
1/2 Bit
1/2 Bit
Bit check ok
Bit check ok
T
XClk
Start-up mode
Bit-check mode
T
Start-up
T
Bit-check
Bit check
IC_ACTIVE
Bit-check-
counter
0
2 3 4 5 6
2
4
5
1
1
3
6 7 8 9
11 12
10
1/2 Bit
Start-up mode
0
( Lim_min = 14, Lim_max = 24 )
Sleep mode
Bit check failed ( CV_Lim < Lim_min )
Dem_out
Bit-check mode
T
Start-up
T
Bit-check
T
Sleep
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| T5743P3-TG | UHF ASK/FSK Receiver |
| T5743P3-TGQ | UHF ASK/FSK Receiver |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T5743P3 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:UHF ASK/FSK Receiver |
| T5743P3-TG | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:UHF ASK/FSK Receiver |
| T5743P3-TGQ | 功能描述:IC RCVR ASK/FSK 300MHZ 20-SOIC RoHS:否 類別:RF/IF 和 RFID >> RF 接收器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 09/Jan/2012 標準包裝:50 系列:* 頻率:850MHz ~ 2.175GHz 靈敏度:- 數(shù)據(jù)傳輸率 - 最大:- 調制或協(xié)議:- 應用:* 電流 - 接收:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 特點:- 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 85°C 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| T5743P3-TGS | 功能描述:IC RCVR ASK/FSK 300MHZ 20-SOIC RoHS:否 類別:RF/IF 和 RFID >> RF 接收器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 09/Jan/2012 標準包裝:50 系列:* 頻率:850MHz ~ 2.175GHz 靈敏度:- 數(shù)據(jù)傳輸率 - 最大:- 調制或協(xié)議:- 應用:* 電流 - 接收:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 特點:- 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 85°C 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| T5743P6-TG | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:UHF ASK/FSK Receiver |
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