參數(shù)資料
型號(hào): T5743
廠商: Atmel Corp.
英文描述: UHF ASK/FSK Receiver
中文描述: 超高頻ASK / FSK接收器
文件頁(yè)數(shù): 26/41頁(yè)
文件大小: 681K
代理商: T5743
26
T5743
4569A–RKE–12/02
Table 11.
Effect of the Configuration Word Lim_min
Lim_min
(1)
(Lim_min < 10 Is Not Applicable)
Note:
1. Lim_min is also be used to determine the margins of the data clock control logic (see section “Data Clock”).
Table 12.
Effect of the Configuration Word Lim_max
Lim_max
(1)
(Lim_max < 12 Is Not Applicable)
Note:
1. Lim_max is also be used to determine the margins of the data clock control logic (see section “Data Clock”).
Conservation of the Register
Information
The T5743 implies an integrated power-on reset and brown-out detection circuitry to
provide a mechanism to preserve the RAM register information.
According to Figure 32
,
a power-on reset (POR) is generated if the supply voltage V
S
drops below the threshold voltage V
ThReset
. The default parameters are programmed into
the configuration registers in that condition. Once V
S
exceeds V
ThReset
the POR is can-
celled after the minimum reset period t
Rst
. A POR is also generated when the supply
voltage of the receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at Pin DATA after a
reset. The RM is represented by the fixed frequency f
RM
at a 50% duty-cycle. RM can be
cancelled via a Low pulse t1 at Pin DATA.
Lower Limit Value for Bit Check
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(T
Lim_min
=
Lim_min
×
Lim
×
T
Clk
)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
0
0
1
1
0
0
12
...
...
...
...
...
...
0
1
0
1
0
1
21 (default)
USA: T
Lim_min
= 342 μs, Europe: T
Lim_min
= 348 μs)
...
...
...
...
...
...
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Upper Limit Value for Bit Check
Lim_max5
Lim_max4
Lim_max3
Lim_max2
Lim_max1
Lim_max0
(T
Lim_max
=
(Lim_max - 1)
×
XLim
×
T
Clk
)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14
...
...
...
...
...
...
1
0
1
0
0
1
41 (default)
USA: T
Lim_max
= 652 s,
Europe: T
Lim_max
= 662 μs)
...
...
...
...
...
...
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
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