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參數(shù)資料
| 型號： | T6A04A |
| 廠商： | Toshiba Corporation |
| 英文描述： | Column and Row Driver LSI for a Dot Matrix Graphic LCD |
| 中文描述： | 列和行驅(qū)動器LSI的點陣圖形液晶顯示器 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 307K |
| 代理商： | T6A04A |
T6A04A
2002-03-06
6
Function of Each Block
Interface logic
The T6A04A can be operated with an 80-Series MPU.
Figure 1 shows an example of the interface.
Input register
This register stores 8-bit data from the MPU. The D/I signal distinguishes between command data and
display data.
Output register
This register stores 8-bit data from the display RAM. When display data is read, the display data specified by
the address in the address counter is stored in this register. After that, the address is automatically
incremented or decremented. Therefore, when an address is set, the correct data does not appear as the first
data item that is read. The data in the specified address location appears as the second data item that is read.
X-address counter
The X-address counter is a 64-up/down counter. It holds the row address of a location in the display RAM.
Writing data to or reading data from the display RAM causes the X-address to be automatically incremented
or decremented.
Y-(page) address counter
The Y-(page) address counter is either a 15-up/down counter, when the word length is eight bits, or a
20-up/down counter, when the word length is six bits. It holds the column address of a location in the display
RAM. Writing data to or reading data from the display RAM causes the Y-address to be automatically
incremented or decremented.
Z-address counter
The Z-address counter is a 64-up counter that provides the display RAM data for the LCD drive circuit. The
data stored in the Z-address register is sent to the Z-address counter as the Z start address.
For instance, when the Z start address is 32, the counter increments as follows: 32, 33, 34 ..., 62, 63, 0, 1, 2 ...
30, 31, 32. Therefore, the display start line is line 32 of the display RAM.
Up/down register
The 1-bit datum stored in this register selects either Up or Down mode for the X-and Y-(page) address
counters.
Counter select register
The 1-bit datum stored in this register selects the X-address counter or Y-(page) address counter.
Display ON/OFF register
This 1-bit register holds the display ON/OFF state. In the OFF state, the output data from the display RAM is
cleared. In the ON state, the display RAM data is displayed. The display ON/OFF state does not affect the data
in the display RAM.
Z-address register
This 6-bit register holds the data which specifies the display start line. The data is loaded into the Z-address
counter on the FRM signal. Using the Z-address register, vertical scrolling is possible.
A0
/IORQ
/WR
<MPU>
D0 to D7
/RESET
D/1
/CE
/WR
<T6A04A>
DB0 to DB7
/RST
Figure 1
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