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參數(shù)資料
| 型號： | T6A04A |
| 廠商： | Toshiba Corporation |
| 英文描述： | Column and Row Driver LSI for a Dot Matrix Graphic LCD |
| 中文描述： | 列和行驅(qū)動器LSI的點陣圖形液晶顯示器 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大小： | 307K |
| 代理商： | T6A04A |
T6A04A
2002-03-06
7
Word length register
The 1-bit datum stored in this register selects the word length: eight bits per word or six bits per word.
Word length change circuit
This circuit is controlled by the word length register. when the word length is eight bits, data is transferred
eight bits at a time. When the word length is six bits, the data transfer method is shown in Figure 2 as follows:
Oscillator
The T6A04A includes an on-chip oscillator. When using this oscillator, connect an external resistor between
OSC1 and OSC2, as shown in Figure 3. When using an external clock, connect the clock input to OSC1 and
leave OSC2 open.
Timing generation circuit
This circuit divides the signals from the oscillator and generates the display timing signals and the operating
clock signal.
Shift register
The T6A04A has two 32-bit shift registers. In disable expansion mode, both the shift registers are enabled.
These two 32-bit shift registers can be combined to form a 64-bit shift register. In enable expansion mode the
32-bit shift register for COM1 to COM32 is enabled in master chip mode, and the 32-bit shift register for
COM33 to COM64 is enabled in slave chip mode.
Latch circuit
The latch circuit latches data from the display RAM on the rising edge of the C
L
signal.
D
4
D
5
*
*
D
3
D
2
D
1
D
0
D
4
D
5
*
*
D
3
D
2
D
1
D
0
Word length
change circuit
Word length
change circuit
D
4
D
5
D
6
D
7
D
3
D
2
D
1
D
0
D
4
D
5
0
0
D
3
D
2
D
1
D
0
*:
INVALID
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Display
RAM
MPU
Figure 2
OSC1
OSC2
Internal Circuit
/STB
Figure 3
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