參數(shù)資料
型號: T71L6816A
廠商: TM Technology, Inc.
英文描述: Sixteen-port 10/100 Switch
中文描述: 16端口10/100交換機
文件頁數(shù): 12/22頁
文件大?。?/td> 820K
代理商: T71L6816A
TE
CH
tm
increasing from 01000b to 01111b after power on reset. The polling process will be
Preliminary T71L6816A
Taiwan Memory Technology, Copy-Right reserved.
P. 12
Change to products or specifications without notice.
Publication Date:Jun. 2001
Revision:0.A
performing continuously to refresh the link status and the link partner’s abilities
such as speed, duplex and flow control until power off.
The following table shows the format of MDIO management frames:
Operation Preamble ST
Read
Write
OP PHYaddr REGaddr
10
AAAAA
01
AAAAA
TA
Z0
10
DATA
IDLE
Z
Z
1……1
1……1
01
01
RRRRR
RRRRR
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
3.17 Interface of 24LC02
3.17.1 Block Diagram
The 24LC02 is an EEPROM chip providing 2K bits storage space with 2-wire I
2
C interface.
After power on reset, the T71L6816A will use a sequential read command to load the
configuration settings defined by user in the 24LC02 and configure the features from
those settings for later normal operation. Once loading completed, the T71L6816A will
tri-state the two pins SDA and SCLK to be ready for on-line updating 24LC02 through the
parallel port.
As shown above, the user can run a simple program on WinNT/Win98 to configure the external
24LC02 through the parallel port which is popular in most personal/notebook computer.
The whole system can then be reset after the external 24LC02 been reconfigured to adapt
for different environments.
相關(guān)PDF資料
PDF描述
T81L0003A Reduced I/O 8-bit MCU
T81L0003A-AK Reduced I/O 8-bit MCU
T81L0003A-BD Reduced I/O 8-bit MCU
T81L0003A-BK Reduced I/O 8-bit MCU
T81L0003A-AD Reduced I/O 8-bit MCU
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