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參數(shù)資料
| 型號： | T71L6816A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | Sixteen-port 10/100 Switch |
| 中文描述： | 16端口10/100交換機 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 820K |
| 代理商： | T71L6816A |
TE
CH
tm
Preliminary T71L6816A
Taiwan Memory Technology, Copy-Right reserved.
P. 17
Change to products or specifications without notice.
Publication Date:Jun. 2001
Revision:0.A
Symbol
I/O type
Pin Number
Function
SRAM Interfaces (Cont.)
SRAM_ADDR[15:0]
O
107, 108, 109, 110,
111, 112, 113, 114,
115, 116, 117, 118,
119, 120, 121, 122
SRAM Address Bus
.
Power Pins
VCC
2, 33, 65, 88, 128,
158, 167
Power Pins for System
.
3.3V DC power.
GND
1, 32, 64, 89, 126,
160, 165, 169, 188
Ground Pin
.
DC ground.
VDD
90, 157, 201
Power Pins for Core
.
1.8V DC power.
Serial EEPROM Interfaces
SCLK
O
172
Serial Clock
.
SCLK is used to synchronize the SDA and to be
pulled high internally.
SDA
I/O
173
Serial Data/Access
.
Bi-directional serial data I/O line which is
pulled high internally.
PHY Management Interfaces
MDC
O
174
PHY
Management Interface Clock
.
The MDC provides the reference clock for shifting
serial data in/out from PHY device on rising
edges.
MDIO
I/O
175
PHY
Management Interface Data I/O
.
Bi-directional serial data contains information
which is read from or written to the PHY devices.
Test Pins
TEST
I
171
Test Mode Enable
.
For normal use, this pin must be tire to low.
MOD[3:0]
I
107, 108, 109, 110
Test Mode Select
.
For normal use, those p ins should be tired to low.
System Interfaces
RST
I
170
Reset
.
Asynchronous active low reset signal.
SYSCLK
I
168
System Clock
.
50MHz clock for system.
PLL_OFF
I
159
Phase-Loop-Lock enable/disable
.
High to disable the internal PLL circuit.
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