參數(shù)資料
型號： T7237A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 82/116頁
文件大?。?/td> 1056K
代理商： T7237A
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
78
Lucent Technologies Inc.
Timing Characteristics
(continued)
Switching Test Input/Output Waveform
5-2118 (C)
Figure 31. Switching Test Waveform
Figure 31 assumes that pin 12 (SDI) is low when
RESET is asserted. The meaning of the setup and hold
times tRSLFL and tFLRSH is as follows.
From the time RESET goes low, the following events
must occur:
1. A falling edge of SYN8K must occur that meets the
setup time with respect to RESET falling edge.
2. At least two additional falling edges of SYN8K (i.e.,
frames) must occur.
3. A falling edge of SYN8K must occur that meets the
hold time with respect to RESET rising edge.
If RESET is asserted asychronously to SYN8K (which
will typically be the case), its falling edge may violate
the setup time with respect to SYN8K. Therefore, an
additional frame time (125
μ
s) will elapse before a
falling edge of SYN8K occurs that will satisfy criterion
#1, above. This means, that to guarantee the RESET
requirements are met for parameter tRSLRSH, RESET
should be held low for a minimum of 500.120
μ
s
(4 frames + 1 setup time + 1 hold time).
Propagation Delay
The maximum propagation delay from the S/T-interface
to the U-interface (upstream direction) is 750
μ
s. The
maximum propagation delay from the U-interface to the
S/T-interface (downstream direction) is 550
μ
s.
2.0 V
0.8 V
2.0 V
0.8 V
TEST POINTS
2.4 V
0.4 V
2.4 V
0.4 V
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