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參數資料
| 型號： | T7504 |
| 元件分類： | Codec |
| 英文描述： | T7504 and T75504 Quad PCM Codecs with Filters |
| 中文描述： | T7504和T75504四的PCM編解碼器與濾波器 |
| 文件頁數： | 2/18頁 |
| 文件大?。?/td> | 221K |
| 代理商： | T7504 |
2
Lucent Technologies Inc.
Data Sheet
March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Functional Description
Four channels of PCM data input and output are
passed through only two ports, D
type of time-slot assignment is necessary. The scheme
used here is to utilize timing modes of 32 or 64 time
slots corresponding to master clock frequencies of
either 2.048 MHz or 4.096 MHz, respectively. Each
device has four transmit frame sync (FS
for each channel. During a single 125
transmit frame sync input is supplied a single pulse.
The timing of the pulse indicates the beginning of the
time slot during which the data for that channel is
clocked out of the device. During a frame, transmit
frame sync pulses must be separated from each other
by one or more time slots. A channel is placed in a
standby (low-power) mode if its FS
for 500
μ
s.
X
and D
R
, so some
X
s frame, each
) inputs, one
μ
X
input has been low
There is a single frame sync separation input (FSEP).
The number of negative clock edges minus one that
occurs while FSEP is high is the delay (in clock
periods) that is placed between the rising edge of a
transmit frame sign bit and the falling edge used by the
receiver to sample the sign bit. There must always be a
pulse on the FSEP input since this input provides the
8 kHz signal required to maintain internal timing. If the
FSEP pulse is one clock period or less, the device
makes the transmit edges and receive sampling edges
one half clock period apart. The entire device is placed
in a powerdown mode if FSEP remains low for 500
μ
s.
Time slot zero is defined as starting on the first rising
MCLK edge after FSEP = 1 is detected by a negative
MCLK edge. In the T7504, MCLK negative-going
edges that detect the start of FSEP and FS
integer multiples of eight MCLK periods apart (zero
multiples are allowed). Since FSEP is assumed to
define time slot 0, the number of multiples separating
FS
X
N and FSEP is the time-slot number. In the T5504,
FS
X
N for time slot 0 nominally starts on the MCLK
positive edge following the negative edge which
detects FSEP.
X
N must be
The frequency of the master clock must be either
2.048 MHz or 4.096 MHz. Internal circuitry determines
the master clock frequency during the powerup reset
interval.
Powerdown is not guaranteed if MCLK is lost unless
the device is already in the powerdown mode due to
FSEP low for at least 500
μ
s.
The analog input section in Figure 2 includes an on-
chip op amp that is used in conjunction with external,
user-supplied resistors to vary encoder passband gain.
The feedback resistance (R
F
to 200 k
and capacitance from GSx to ground should
be kept to less than 50 pF. The input signal at VF
should be ac coupled. For best performance, the maxi-
mum gain of this op amp should be limited to 20 dB or
less.
) should range from 10 k
X
IN
5-3786
Figure 2. Typical Analog Input Section
VF
X
IN
TO
CODEC
FILTERS
2.4 V
GAIN =
R
X
R
I
GS
X
R
I
R
F
–
+
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相關代理商/技術參數 |
參數描述 |
|---|---|
| T7507 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance |
| T75-08M2 | 制造商:The Cherry Corporation 功能描述: |
| T-751 | 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:Fly Back Transformer |
| T75-24C3 | 制造商:Stancor 功能描述:Power Transformer Triple Prim. Single Sec. 120V/208V/240V Prim. 24V Sec. Flange Mount |
| T7570 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T7570 Programmable PCM Codec with Hybrid-Balance Filter |
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