TE
CH
tm
!
Refreshing the watchdog timer
T81L0003A
TM Technology, Inc. reserves the right
P. 15
to change products or specifications without notice. Revision: C
Publication Date: SEP. 2004
The watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. This requirement
imposes obligation on the programmer to issue two followed instructions. The first instruction sets
wdt
and the second one
swdt
. The maximum allowed delay between settings of the
wdt
and
swdt
is 12 instruction cycles. While this period has
expired and
swdt
has not been set,
wdt
is automatically reset, otherwise the watchdog timer is reloaded with the content of
the
wdtrel
register and
wdt
is automatically reset. The procedure is as “Start procedure” before.
!
Special Function Registers
a) Interrupt Enable 0 register (ien0)
The ien0 register (address : A8)
MSB
LSB
eal
wdt
et2
es0
et1
ex1
et0
ex0
The ien0 bit functions
Bit
Symbol
Function
ien0.6
wdt
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before swdt is set to
prevent an unintentional refresh of the watchdog timer. The wdt is reset by hardware 12
instruction cycles after it has been set.
Note: other bits are not used to watchdog control
b) Interrupt Enable 1 register (ien1)
The ien1 register (Address : B8)
MSB
LSB
-
swdt
pt2
ps
pt1
px1
pt0
px0
The ien1 bit functions
Bit
Symbol
Function
Ien1.6
swdt
Watchdog timer start refresh flag.
Set to active/refresh the watchdog timer. When directly set after setting wdt, a watchdog
timer refresh is performed. Bit swdt is reset by hardware 12 instruction cycles after it has
been set.
Pay attention that when write ien1.6, it write the swdt bit, when read ien1.6, we will read out the wdts bit. Ie. Watch
dog timer status flag. Set by hardware when the watchdog timer was started.