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參數(shù)資料
| 型號： | T81L0003A-AK |
| 廠商： | TM Technology, Inc. |
| 英文描述： | Reduced I/O 8-bit MCU |
| 中文描述： | 減少的I / O 8位微控制器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 113K |
| 代理商： | T81L0003A-AK |
TE
CH
tm
Program Status Word
T81L0003A
TM Technology, Inc. reserves the right
P. 7
to change products or specifications without notice. Revision: C
Publication Date: SEP. 2004
The PSW register contains program status information as detailed in
MSB
LSB
CY
AC
F0
RS1
RS0
OV
--
P
BIT SYMBOL FUNCTION
PSW.7 CY Carry flag.
PSW.6 AC Auxilliary Carry flag. (For BCD operations.)
PSW.5 F0 Flag 0. (Available to the user for general purposes.)
PSW.4 RS1 Register bank select control bit 1.
Set/cleared by software to determine working register bank. (See Note.)
PSW.3 RS0 Register bank select control bit 0.
Set/cleared by software to determine working register bank. (See Note.)
PSW.2 OV Overflow flag.
PSW.1 — User-definable flag.
PSW.0 P Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even number of “one” bits in the
Accumulator, i.e., even parity.
NOTE: The contents of (RS1, RS0) enable the working register banks as follows:
(0,0)— Bank 0 (00H–07H)
(0,1)— Bank 1 (08H–0fH)
(1,0)— Bank 2 (10H–17H)
(1,1)— Bank 3 (18H–1fH)
Stack Pointer
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions.
While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the
stack to begin at locations 08H.
Data Pointer (DPTR)
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a
16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 1.0-1.7 & 3.0-3.4
All Ports are the SFR latches, respectively. Writing a one to a bit of a port SFR (P1 or P3) causes the corresponding
port output pin to switch high. Writing a zero causes the port output pin to switch low. When used as an input, the external
state of a port pin will be held in the port SFR (i.e., if the external state of a pin is low, the corresponding port SFR bit will
contain a ‘0’; if it is high, the bit will contain a ‘1’).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T81L0003A-BD | Reduced I/O 8-bit MCU |
| T81L0003A-BK | Reduced I/O 8-bit MCU |
| T81L0003A-AD | Reduced I/O 8-bit MCU |
| T81L0003B | 8-bit MCU |
| T81L0003B-AD | 8-bit MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T81L0003A-BD | 制造商:TMT 制造商全稱:TMT 功能描述:Reduced I/O 8-bit MCU |
| T81L0003A-BK | 制造商:TMT 制造商全稱:TMT 功能描述:Reduced I/O 8-bit MCU |
| T81L0003B | 制造商:TMT 制造商全稱:TMT 功能描述:8-bit MCU |
| T81L0003B-AD | 制造商:TMT 制造商全稱:TMT 功能描述:8-bit MCU |
| T81L0003B-AK | 制造商:TMT 制造商全稱:TMT 功能描述:8-bit MCU |
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