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參數(shù)資料
| 型號(hào)： | T835-XXXH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8A TRIACS |
| 中文描述： | 8A條雙向可控硅 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | T835-XXXH |
BTA08, BTB08 and T8 Series
5/11
Figure 7: Non-repetitive surge peak on-state
current for a sinusoidal pulse with width t
p
< 10 ms
and corresponding value of I
2
t
Figure 8: Relative variation of gate trigger
current, holding current and latching current
versus junction temperature (typical values)
Figure 9: Relative variation of critical rate of
decrease of main current versus (dV/dt)c
(typical values) (Snubberless & Logic level
types)
Figure 10: Relative variation of critical rate of
decrease of main current versus (dV/dt)c
(typical values) (Standard types)
Figure 11: Relative variation of critical rate of
decrease of main current versus junction
temperature
Figure 12:
DPAK and D
2
PAK Thermal resistance
junction to ambient versus copper surface under
tab (printed circuit board FR4, copper thickness:
35 μm)
0.01
0.10
1.00
10.00
10
100
1000
I
(A), I t (A s)
TSM
2
2
t (ms)
T initial=25°C
j
I
TSM
dI/dt limitation:
50A/μs
I t
2
-40
-20
0
20
40
60
80
100
120
140
0.0
0.5
1.0
1.5
2.0
2.5
T (°C)
I
GT H L
j
I
GT H L
j
I
GT
I
H
& I
L
0.1
1.0
10.0
100.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
(dV/dt)c (V/μs)
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
TW
T835/CW/BW
T810/SW
0.1
1.0
10.0
100.0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
(dV/dt)c (V/μs)
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
C
B
0
25
50
75
100
125
0
1
2
3
4
5
6
(dI/dt)c [T ] /
pecified]
(dI/dt)c [T s
T (°C)
0
4
8
12
16
20
24
28
32
36
40
0
10
20
30
40
50
60
70
80
90
100
S(cm2)
R
(°C/W)
th(j-a)
D PAK
DPAK
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| T8XX-XXXB | 8A TRIACS |
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| T8XX-XXXH | 8A TRIACS |
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